An FPGA prototype for a multiplierless FIR filter built using the logarithmic number system
This paper describes the development of a prototype 64-tap multiplierless FIR filter based on the Logarithmic Number System (LNS). The circuit has been implemented and tested using a single Xilinx X64C64 device with external coefficient memory, data memory, ADC and DAC. The filter samples at 14KHz and runs at a rate of 895KHz (64 × 14KHz). This architecture is suitable for implementation using custom VLSI and can provide a compact, low-power solution to a number of simple filtering problems. It can also be expanded or cascaded to produce higher order filters.
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