FPLD-implementation of computations over finite fields GF(2m) with applications to error control coding

  • André Klindworth
Arithmetic and Signal Processing
Part of the Lecture Notes in Computer Science book series (LNCS, volume 975)


This paper investigates the implementation of computations over finite fields GF(2m) using field-programmable logic devices (FPLDs). Implementation details for addition/subtraction, multiplication, square, inversion, and division are given with mapping results for Xilinx LCAs, Altera CPLDs and Actel ACT FPGAs. As an application example, mapping results for complete encoders for error-correcting codes are also presented. Finally, new opportunities emerging from FPLD technology for data transmission systems with dynamic code adaption are discussed.


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  1. 1.
    T. C. Bartee and D. I. Schneider, Computation with finite fields, Inform. Contr., vol. 6, pp.79–98, Mar. 1963.Google Scholar
  2. 2.
    E. R. Berlekamp, Algebraic Coding Theory, New York: McGraw-Hill, 1968.Google Scholar
  3. 3.
    E.R. Berlekamp, The Technology of Error-Correcting Codes, Proc. IEEE, vol.68, pp.564–593, May 1980.Google Scholar
  4. 4.
    R. E. Blahut, Theory and practice of error control codes, Addison-Wesley, 1983.Google Scholar
  5. 5.
    R. K. Brayton et al., MIS: A Multiple-Level Logic Optimization System, IEEE Trans. on Computer Aided-Design, CAD-6(6), pp. 1062–1081, Nov. 1987Google Scholar
  6. 6.
    R. Lidl and H. Niederreiter, Introduction to finite fields and their applications, London, New York: Cambridge University Press, 1986Google Scholar
  7. 7.
    E. D. Mastrovito, VLSI designs for computations over finite fields GF(2m), Ph.D. Thesis No.159, Dept.of Electr. Engineering, Linköping Univ., Sweden, Dec. 1988.Google Scholar
  8. 8.
    R. J. McEliece, Finite Fields for Computer Scientists and Engineers, Boston,MA: Kluwer Academic Publishers, 1987.Google Scholar
  9. 9.
    P. J. McWilliams and N. J. A. Sloane, The Theory of Error-Correcting Codes, Amsterdam: North-Holland, 1978.Google Scholar
  10. 10.
    H. Hoeve, J. Timmermans and L. B. Vries, Error correction and concealment in the Compact Disk system, Philips tech. Rev. 40, No. 6, 1982.Google Scholar
  11. 11.
    J.-L. Politano and D. Deprey, A 30 Mbits/s (255,223) Reed-Solomon Decoder, EUROCODE '90, Int't Symp. on Coding Theory and Applications, Udine, Italy, Nov. 1990.Google Scholar
  12. 12.
    H. C. A. van Tilborg, An Introduction to Cryptology; Boston, MA; Kluwer Academic Publishers, 1988.Google Scholar
  13. 13.
    C. C. Wang et. al., VLSI Architectures for Computing Multiplications and Inverses in GF(2m), IEEE Trans. Comput., vol. C-34, pp.709–717, Aug. 1985.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1995

Authors and Affiliations

  • André Klindworth
    • 1
  1. 1.Dept. of Computer ScienceUniversity of HamburgHamburgGermany

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