Delay minimal mapping of RTL structures onto LUT based FPGAs
This paper presents an approach for mapping data paths onto FPGAs minimizing delay. The approach exploits the regularity of data path components. It involves slicing the components and generating ”realizable cones” from slices of one or more connected components. The objective in delay minimization is to cover the RTL structure with realizable cones in such a way that the maximum path length is minimized. A parameter called delay benefit is defined for each cone based on its potential to reduce the path delay. A greedy heuristic is employed to cover the current critical path with cones having maximal delay benefit. Experimental results are shown to demonstrate delay reduction obtained by this approach.
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