Abstract
In this paper, we present the formalization and the validation of memory protocols for multiprocessor architectures. Memory access is supposed to be atomic and can be observed by all the processors of the architecture. We first introduce a framework for the specification and the validation by refinements of parallel programs. For this purpose, we propose a new state representation allowing strong typing. After introducing refinements in the context of transition systems, we validate some refinement properties of sequential and parallel statements. At last, we define a representation of multiprocessor cache protocols exploiting the symmetry of such algorithms and show its correctness.
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Bodeveix, J.P., Filali, M. (1995). On the refinement of symmetric memory protocols. In: Thomas Schubert, E., Windley, P.J., Alves-Foss, J. (eds) Higher Order Logic Theorem Proving and Its Applications. TPHOLs 1995. Lecture Notes in Computer Science, vol 971. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60275-5_57
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DOI: https://doi.org/10.1007/3-540-60275-5_57
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