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A VLSI system for neural Bayesian and LVQ classification

  • Philippe Thissen
  • Michel Verleysen
  • Jean-Didier Legat
  • Jordi Madrenas
  • Jordi Domínguez
Implementation
Part of the Lecture Notes in Computer Science book series (LNCS, volume 930)

Abstract

Various types of neural networks may be used in multi-dimensional classification tasks; among them, Bayesian and LVQ algorithms are interesting respectively for their performances and their simplicity of operations. The large number of operations involved in such algorithms may however be incompatible with on-line applications or with the necessity of portable small-size systems. This paper describes a neural network classifier system based on a fully analog operative chip coupled with a digital control system. The chip implements sub-optimal Bayesian classifier and LVQ algorithms.

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References

  1. [1]
    P. Comon, G. Bienvenu, and T. Lefebvre, “Supervised design of optimal receivers”, in NATO Advanced Study Institute on Acoustic Signal Processing and Ocean Exploration, Madeira, Portugal, July 26–Aug. 7 1992.Google Scholar
  2. [2]
    J.L. Voz, M. Verleysen, P. Thissen, and J.D. Legat, “Handwritten digit recognition by suboptimal bayesian classifier”, in NeuroNîmes94 (Neural Networks and their applications). October 1994, EC2, submitted.Google Scholar
  3. [3]
    T. Kohonen, Self-Organization and Associative Memory, Springer-Verlag, Berlin, 1989, 3rd Edition.Google Scholar
  4. [4]
    T. Cacoullos, “Estimation of a multivariate density”, Annals of Inst. Stat. Math., vol. 18, pp. 178–189, 1966.Google Scholar
  5. [5]
    E. Parzen, “On the estimation of a probability density function and the mode”, Ann. Math. Stat., vol. 27, pp. 1065–1076, 1962.Google Scholar
  6. [6]
    Q. Xie, C. A. Laszlo, and R. K. Ward, “Vector quantization technique for nonparametric classifier design”, IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 15, no. 12, pp. 1326–1330, december 1993.Google Scholar
  7. [7]
    M. Verleysen, P. Thissen, J.L. Voz, and J. Madrenas, “An analog processor architecture for neural network classifier”, IEEE Micro, vol. 14, no. 3, pp. 16–28, June 1994.Google Scholar
  8. [8]
    D. Macq, J.D. Legat, and P. Jespers, “Analog storage of adjustable synaptic weights”, in Proceedings of the SPIE conference on Applications of Artificial Neural Networks, Orlando (USA), April 1992, pp. 712–718.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1995

Authors and Affiliations

  • Philippe Thissen
    • 1
  • Michel Verleysen
    • 1
  • Jean-Didier Legat
    • 1
  • Jordi Madrenas
    • 2
  • Jordi Domínguez
    • 2
  1. 1.Laboratoire de Microélectronique - DICEUniversité catholique de LouvainLouvain-La-NeuveBelgium
  2. 2.Departament d'Enginyeria ElectrònicaUniversitat Politècnica de CatalunyaBarcelonaSpain

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