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Studies of the single pulser in various reasoning systems

  • Steven D. Johnson
  • Paul S. Miner
  • Albert Camilleri
Research Papers
Part of the Lecture Notes in Computer Science book series (LNCS, volume 901)

Abstract

The single pulser is a clocked sequential device which generates a unit-time pulse on its output for every pulse on its input. This paper explores how a single-pulser implementation is verified by various formal reasoning tools, including the PVS theorem prover for higher-order logic, the SMV model checker for computation tree logic, the DDD design derivation system, and the Oct Tools design environment. By fixing a single, simple example, the study attempts to contrast how the underlying formalisms influence one's perspective on design and verification.

Keywords and Phrases

Formal methods hardware verification formal verification theorem prover higher order logic model checker design derivation logic synthesis PVS SMV CTL DDD Oct Tools 

References

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    Further details about these studies can be obtained through the World Wide Web via URL www.cs.indiana.edu. Access the Single Pulser Study through the Hardware Methods Group thread in the list of departmental research projects. Individuals wishing to contribute to this collection should contact sjohnson@cs.indiana.edu or write Hardware Methods Laboratory, Indiana University Computer Science Department, Bloomington Indiana, USA.Google Scholar
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Copyright information

© Springer-Verlag Berlin Heidelberg 1995

Authors and Affiliations

  • Steven D. Johnson
    • 1
  • Paul S. Miner
    • 2
  • Albert Camilleri
    • 3
  1. 1.Indiana UniversityBloomingtonUSA
  2. 2.NASA Langley Research CenterHamptonUSA
  3. 3.Hewlett-Packard CompanyRosevilleUSA

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