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An automatic generalization method for the inductive proof of replicated and parallel architectures

  • Laurence Pierre
Research Papers
Part of the Lecture Notes in Computer Science book series (LNCS, volume 901)

Abstract

Our approach for verifying the equivalence of two VHDL architectures consists in translating these descriptions into functional forms and then in proving the equivalence of these functions. As far as replicated or parallel architectures are concerned, an induction-based method is used for verifying generic n-bit descriptions. This technique takes advantage of the regular structure of these devices and can give better results than the BDD-based approaches. However, induction requires complete specifications, whereas the designers usually supply partial specifications. Therefore, we propose a specialized automatic method for generalizing such incomplete statements, before the Boyer-Moore proof process.

References

  1. [1]
    P. ASHAR, A. GHOSH, S. DEVADAS, A. NEWTON: “Combinational and sequential logic verification using general binary decision diagrams”. Proc. Int. Workshop on Logic Synthesis, Research Triangle Park (NC), May 1991.Google Scholar
  2. [2]
    R. AUBIN: “Mechanizing structural induction-Part II: Strategies”. Theoretical Computer Science 9. North-Holland, 1979. pp. 347–362.Google Scholar
  3. [3]
    R.S. BOYER, J. S. MOORE: “A Computational Logic”. ACM Monograph Series. Academic Press, Ins. 1979.Google Scholar
  4. [4]
    R.S. BOYER, J. S. MOORE: “A Computational Logic Handbook”. Perspectives in Computing, Vol. 23. Academic Press, Inc. 1988.Google Scholar
  5. [5]
    D. BORRIONE, L. PIERRE, A. SALEM: “Formal Verification of VHDL Descriptions in the PREVAIL Environment”. IEEE Design&Test magazine, vol. 9, n∘2, June 1992.Google Scholar
  6. [6]
    R.E. BRYANT: “Graph-based Algorithms for Boolean Function Manipulation”. IEEE Transactions on Computers, Vol. C-35, n∘8, August 1986.Google Scholar
  7. [7]
    R.E. BRYANT: “On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication”. IEEE Transactions on Computers, Vol. 40, n∘2, February 1991.Google Scholar
  8. [8]
    J.R. BURCH: “Using BDDs to verify multipliers”. Proc. DAC'91, San Francisco (CA), June 1991.Google Scholar
  9. [9]
    P. CAMURATI, P. PRINETTO: “Formal Verification of Hardware Correctness: Introduction and Survey of Current Research”. IEEE Computer, Vol. 21, n∘7. July 1988.Google Scholar
  10. [10]
    M. FUJITA, H. FUJISAWA, N. KAWATO: “Evaluation and Improvements of Boolean Comparison Method based on Binary Decision Diagrams”. Proc. Int. Conference on Computer-Aided Design ICCAD'88, 1988.Google Scholar
  11. [11]
    W.A. HUNT: “FM8501: A verified microprocessor”. Institute for Computing Science, University of Texas, Austin (USA). Technical Report n∘47. February 1986.Google Scholar
  12. [12]
    K. HWANG: “Computer arithmetic: principles, architecture and design”, John Wiley & sons Inc., New-York, 1979.Google Scholar
  13. [13]
    IEEE Standard VHDL Language Reference Manual, IEEE. 1988.Google Scholar
  14. [14]
    T. KROPF: “Benchmark-Circuits for Hardware Verification, 2nd TPCD Conference”. 2nd Conference on Theorem Proving in Circuit Design, Bad Herrenalb (Germany), 1994.Google Scholar
  15. [15]
    J.S. MOORE: “Introducing Iteration into the Pure Lisp Theorem Prover”. IEEE Transactions on Software Engineering, Vol. SE-1, n∘3. September 1975.Google Scholar
  16. [16]
    Z. MANNA, R. WALDINGER: “Knowledge and Reasoning in Program Synthesis”. Artificial Intelligence Journal. Vol. 6, 2. 1975.Google Scholar
  17. [17]
    S. MALIK, A.R. WANG, R.K. BRAYTON, A. SANGIOVANNI-VINCENTELLI: “Logic Verification using Binary Decision Diagrams in a Logic Synthesis Environment”. Proc. Int. Conference on Computer-Aided Design ICCAD'88, 1988.Google Scholar
  18. [18]
    L. PIERRE: “The Formal Proof of the Min-Max sequential benchmark described in CASCADE using the Boyer-Moore Theorem Prover”. Proc. IFIP WG 10.2 Int. Workshop Nov. 1989. In “Formal VLSI Correctness Verification”, L. Claesen ed., North Holland, 1990.Google Scholar
  19. [19]
    L. PIERRE: “One Aspect of Mechanizing Formal Proof of Hardware: the Generalization of Partial Specifications”. Proc. ACM International Workshop on Formal Methods in VLSI Design. Miami (Fl). 9–11 January 1991.Google Scholar
  20. [20]
    L. PIERRE: “VHDL Description and Formal Verification of Systolic Multipliers”. In “CHDL and their Applications”, D. Agnew, L. Claesen & R. Camposano Eds., North Holland, 1993.Google Scholar
  21. [21]
    H. SIMONIS: “Formal verification of multipliers”. Proc. IFIP WG 10.2 Int. Workshop Nov. 1989. In “Formal VLSI Correctness Verification”, L. Claesen ed., North Holland, 1990.Google Scholar
  22. [22]
    D. VERKEST, L. CLAESEN, H. DE MAN: “Special Benchmark Session on Formal System Design”. Proc. IFIP WG 10.2 Int. Workshop Nov. 1989. In “Formal VLSI Correctness Verification”, L. Claesen ed., North Holland, 1990.Google Scholar
  23. [23]
    F. WAGNER: “Prevail-DM: a framework-based environment for formal hardware verification”. In “CHDL and their Applications”, D. Agnew, L. Claesen & R. Camposano Eds., North Holland, 1993.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1995

Authors and Affiliations

  • Laurence Pierre
    • 1
  1. 1.Laboratoire d'Informatique de Marseille-URA CNRS 1787CMI/Université de Provence Technopôle de Château-GombertMarseille Cedex 13France

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