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Implementational issues for verifying RISC-pipeline conflicts in HOL

  • Sofiène Tahar
  • Ramayya Kumar
Invited Paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 859)

Abstract

We outline a general methodology for the formal verification of instruction pipelines in RISC cores. The different kinds of conflicts, i. e. resource, data and control conflicts, that can occur due to the simultaneous execution of the instructions in the pipeline have been formally specified in HOL. Based on a hierarchical model for RISC processors, we have developed a constructive proof methodology, i.e. when conflicts at a specific abstraction level are detected, the conditions under which these occur are generated and explicitly output to the designer, thus easing their removal. All implemented specifications and tactics are kept general, so that the implementation could be used for a wide range of RISC cores. In this paper, the described formalization and proof strategies are illustrated via the DLX RISC processor.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Sofiène Tahar
    • 1
  • Ramayya Kumar
    • 2
  1. 1.Institute of Computer Design and Fault ToleranceUniversity of KarlsruheKarlsruheGermany
  2. 2.Department of Automation in Circuit DesignForschungszentrum InformatikKarlsruheGermany

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