Self-timed communication strategies for massively parallel systolic architectures
Self-timing provides an attractive alternative to synchronous design in order to overcome scalability problems and fixed processing time. The self-timed approach abolishes the need for a clock signal at any level in the system, and instead uses local control mechanisms to ensure the circuit behaves correctly independent of communication delays. This paper introduces self-timed design strategies developed for use in massively parallel array architectures. These strategies promote bit-serial elastic control and data communication in scalable array architectures. A number of different solutions will be proposed and are assessed on a cost/performance basis resulting on application driven guidelines for design of communication strategies.
KeywordsScalable Self-timing Bit-serial Elastic Massively-Parallel
Unable to display preview. Download preview PDF.
- 1.Seitz, C.: “System Timing”, in C. Mead and L. Conway, Introduction to VLSI systems, Addison-Wesley, 1980, pp. 218–262.Google Scholar
- 2.Hatamian, M., et al: “Understanding Clock Skew in Synchronous Systems”, Concurrent Computations 1988, pp. 87–96Google Scholar
- 3.Meng, T.: “Synchronization Design For Digital Systems”, Kluwer Academic Publishers 1991.Google Scholar
- 4.Lloyd, D., et al: “Self-Timed Fine Grained Parallel Processing Array Design”, The Workshop on High Performance Special Purpose Architectures, International Symposium on Computer Architecture, Hamilton Island, Australia, 23 May 1992.Google Scholar
- 5.Neilsen, C., et al: “Potential Performance Advantages of Delay-Insensitivity”, Presented at IFIP workshop on Silicon Architectures for neural nets, St. Paul-de-Vence, France, (Nov 1990).Google Scholar
- 6.David, I., et al: “An efficient Implementation of Boolean Functions As Self-Timed Circuits”, Technion and Israel Institute of Technology, 1989.Google Scholar
- 7.Dean, M., et al: “Efficient Self-Timing with Level-Encoded 2-Phase Dual-Rail (LEDR)”, MIT Conference on Advanced Research in VLSI, March 1991.Google Scholar
- 8.Lang, H., et al: “ISA and SISA: Two variants of a general purpose array structure”, Proc. Second International Conference on Supercomputing, Vol. 1, pp. 460–467, 1987.Google Scholar
- 9.Schroder, H., et al: “Instruction Systolic Array-tradeoff between flexibility and speed”, Computer System Science and Engineering, Vol. 3 No. 2, (April 1988), pp. 83–90.Google Scholar
- 10.Hogg, R., et al: “Using Occam and Transputers to Emulate Asynchronous Self-Timed Array Processors”, Proceedings of the 15th International Conference on Information Technology Interfaces 1993, ISSN 1330–1012, pp. 257–262.Google Scholar