Modeling cache coherence overhead with geometric objects

  • R. Kattner
  • M. Eger
  • C. Müller-Schloer
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 854)


In single bus, shared memory multiprocessors with private caches, the cache coherence problem affects the system design at various levels. This paper analyzes which hardware and workload components have the most significant influence on the cache coherence overhead and, therefore, need to be considered when designing the multiprocessor architecture. Subsequently, we incorporate these parameters (i.e., the cache coherence protocol, the cache coherence block size and the sharing of data inherent in the parallel workload) into a model by using a finite state machine. This model also allows a fast and thorough evaluation of the sharing behavior of parallel applications.

Index Terms

Shared memory multiprocessor modeling cache coherence verhead cache coherence block size geometric objects 


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Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • R. Kattner
    • 1
  • M. Eger
    • 1
  • C. Müller-Schloer
    • 1
  1. 1.Institut für Rechnerstrukturen und BetriebssystemeUniversität HannoverHannoverGermany

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