Systematic approach and software tool for systolic design

  • S. G. Sedukhin
  • I. S. Sedukhin
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 854)


A systematic approach and software tool for synthesis and analysis of a set of systolic array processors are presented. The s4Cad tool allow us to obtain and examine the set of admissible array processors. The tool uses advanced graphical media technologies that gets more comfort for the user to evaluate and choose an optimal solution observing the requirements on the computing time, number of processing elements, connections topology, data flow formats, etc. As an example the design of systolic array processors for the transitive closure algorithm is shown.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    A.Benani, Y.Robert. Space-time-minimal systolic arrays for Gaussian elimination and the algebraic path problem. Parallel Computing. No.15.-1990.-pp. 211–225.Google Scholar
  2. 2.
    W.Burleson, B.Jang. ARREST: an interactive graphic analysis tool for VLSI arrays. Proc. Int. Conf. on Application Specific Array Processors. Aug. 4–7, 1992, Berkley, Calif. IEEE Comp. Society.-1992.-pp. 149–162.Google Scholar
  3. 3.
    A.Darte. Regular partitioning for synthesing fixed-size systolic arrays. Technical Report 91-10. Ecole Normale Superiore de Lyon. April.-1991.Google Scholar
  4. 4.
    C.Dezan, H.Le Verge, P.Quinton, Y.Saouter. Alpha du Centaur environment. In P.Quinton and Y.Robert eds., Int. Workshop Algorithms and Parallel VLSI Architectures II. Bonas. France. June.-1991.-pp. 325–334.Google Scholar
  5. 5.
    C.-H.Huang, C.Lengauer. The derivation of systolic implementations of programs. Acta Informatica 24.-1987.-pp. 595–632.Google Scholar
  6. 6.
    P.P.Hou, R.M.Ownes, M.J.Irwin. DECOMPOSER: a synthesizer for systolic systems. Proc. 25th ACM/IEEE Int. Conf. Automatic Design. Anaheim. June 12–15. 1988. N.Y.-1988.-pp. 650–653.Google Scholar
  7. 7.
    S.Y.Kung, S.N.Jean Jack. Array compiler design for VLSI/WSI systems. Proc. of Int. Conf. on Systolic Arrays. Killarney. Co.Kerry. Ireland.-1989.-pp. 665–679.Google Scholar
  8. 8.
    S.Y.Kung, S.C.Lo, P.S.Lewis. Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems. IEEE Trans. on Computers Vil. C-36, No.5-1987.-pp. 603–614.Google Scholar
  9. 9.
    C.Lengauer, M.Barnett, D.G.Hudson. Towards systolizing compilation. Distributed Computing. Vol.5, No.1.-1991.-pp. 7–24.Google Scholar
  10. 10.
    D.I.Moldovan. ADVIS: a software package for the design of systolic arrays. IEEE Trans. on Computer-Aided Design. Vol.6, No.1.-1987.-pp. 33–40.Google Scholar
  11. 11.
    C.Mongenet, G.R.Perrin. Synthesis of systolic arrays for inductive problems. Lecture Notes in Computer Science. No.365. Springer-Verlag.-1989.-pp. 260–277.Google Scholar
  12. 12.
    B.M.Maggs, S.A.Plotkin. Minimum-cost spanning tree as a path finding problem. Information Processing Letters.-1988.-Vol.26.-pp. 291–293.Google Scholar
  13. 13.
    E.T.Omtizigt. SYSTARS: a CAD tool for the synthesis and analysis of VLSI systolic/wavefront arrays. Proc. Int. Conf. Systolic Arrays. San Diego. Calif. May 25–27. 1988. Washington D.C.-1988.-pp. 383–391.Google Scholar
  14. 14.
    P.Quinton, P.Frison, P.Gachet. Synthesing systolic arrays using DIASTOL. VLSI Signal Processing II. IEEE Press.-1986.-pp. 93–105.Google Scholar
  15. 15.
    P.Quinton. The systematic design of systolic arrays. IRISA Internal Report. No.216. INRIA.-1983.Google Scholar
  16. 16.
    S.V.Rajopadhye. Synthesing systolic arrays with control signals from recurrence equations. Distributed Computing. No.3.-1989.-pp. 88–105.Google Scholar
  17. 17.
    T.Risset, Y.Robert. Synthesis of processor arrays for the algebraic path problem: unifying old results and deriving new architectures. Parallel Processing Letters. Vol.1, No.1.-1991.-pp. 19–28.Google Scholar
  18. 18.
    S.G.Sedukhin. Design and analysis of systolic algorithms and structures. Russian Software. No.2.-1991.-pp. 20–40. (in Russian)Google Scholar
  19. 19.
    S.G.Sedukhin. Design and analysis of systolic algorithms for the algebraic path problem. Computers and Artificial Intelligence. Vol.11, No.3.-1992.-pp. 269–292.Google Scholar
  20. 20.
    S.G.Sedukhin, I.S.Sedukhin. Systematic Approach and Software Tool for Systolic Design. Technical Report 93-1-010. The University of Aizu, Japan.-1993.Google Scholar
  21. 21.
    V.VanDongen, M.Petit. PRESAGE: a tool for the parallelization of nested loop programs. Formal VLSI Specification and Synthesis. VLSI Design Methods I. North-Holland.-1990.-pp. 341–359.Google Scholar
  22. 22.
    J.Xue, C.Lengauer. The systematic derivation of control signals for systolic arrays. Report of the Department of Computer Science of the University of Edinburgh. ECS-LFCS-91-152.-1991.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • S. G. Sedukhin
    • 1
  • I. S. Sedukhin
    • 1
  1. 1.The University of AizuFukushimaJapan

Personalised recommendations