Concurrent error detection in fast FNT networks
For many real-time and scientific applications, it is desirable to perform signal and image processing algorithms by means of special hardware in very high speed. With the advent of VLSI technology. large collections of processing elements can be used to achieve high-speed computations. In such designs, some level of fault tolerance must be obtained to ensure the validity of the results. Fermat number transforms (FNT's) are attractive for the implementation of digital convolution because the computations are carried out in modular arithmetic which offer three advantages: no round-off error, no multiplications in the transform, and decomposition into fast algorithm analogous to the FFT. In this paper we present a fault-detectable array architecture for the fast implementation of Fermat number transform. The results show that the design offers concurrent error detection (CED) using very low hardware and time overheads.
Index TermsArray processor fault-tolerance digital signal processing Fermat number transform VLSI
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