Zero aliasing compression based on groups of weakly independent outputs in circuits with high complexity for two fault models

  • Peter Böhlau
Session 7: Built-in self test
Part of the Lecture Notes in Computer Science book series (LNCS, volume 852)


The goal of the presentation is the development of a suboptimal procedure for the solution of a high complexity problem, namely the minimal selection of the groups of weakly independent outputs for large combinational circuits. The knowledge about the groups of weakly independent outputs is usable to reduce both the necessary number of output check bits for the built-in self-test in the average more than 80% with respect to the zero aliasing and the gate area of a self-testing error detecting circuit. It is demonstrated the deductive relationship between the weak independence and the partially self-checking property of the accompanying subcircuit and the relationship between the partially selfchecking property and the groupability property. For the test of this structurally realized functional property in a circuit graph, reduction operations and distance operators for a given circuit graph were used. The results for stuck-at and stuck-open faults are discussed by means of the combinational ISCAS 85 benchmarks.

Index Terms

built-in self-test zero aliasing self-testing circuits functional properties groupability weakly independent outputs 


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  1. 1.
    Böhlau, P.: ”Eine Dekompositionsstrategie für den Logikentwurf auf der Basis funktionstypischer Eigenschaften”, Dissertation A, TU Chemnitz, 1987Google Scholar
  2. 2.
    Böhlau, P.: ”Design of self-checking circuits for unsystematic codes”, Proc. 36th Midwest Symposium on Circuit and Systems, Detroit, USA, 15.–18. 8. 1993, pp. 542–545Google Scholar
  3. 3.
    Gupta, S. K. Pradhan, D. K.; Reddy, S. M.: ”Zero aliasing compression”, Proc. of 20th FTCS'90, pp. 254–263, Newcastle Upon Tyne, UK, 26.–28. 6. 1990Google Scholar
  4. 4.
    Pancholy, A.; Rajski, J.; McNaughton, L. J.: ”Empirical Failure Analysis and Validation of CMOS VLSI Circuits”, Design &: Test of Computers, IEEE, march 1992, pp. 72–83Google Scholar
  5. 5.
    Pomeranz, I.; Reddy, S. M.; Tangirala, R.: ”On achieving zero aliasing for modeled faults”, Proc. of EDAC'92, pp. 291–299, Brussels 1992Google Scholar
  6. 6.
    Pradhan, D. R.:”Fault tolerant computing, theory and techniques”, Printice Hall, Englewood Cliffs, New Jersey, 1986Google Scholar
  7. 7.
    Pradhan, D. K.; Gupta, S. K.: ”A new framework for design and analyzing BIST techniques and zero aliasing compression”, IEEE Transactions on Computers, vol. 40, no. 6, pp. 743–763, June 1991CrossRefGoogle Scholar
  8. 8.
    Rao, T. R. N.; Fujiwara, E.: ”Error-control coding for computer systems”, Printice Hall, Englewood Cliffs, New Jersey, 1989Google Scholar
  9. 9.
    Sogomonyan, E. S.; Gössel, M.:”Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs”, Journal of Electronic Testing, vol. 4, pp. 267–281, 1993CrossRefGoogle Scholar
  10. 10.
    Sogomonyan, E. S.: ”Design of Single-output self-checking check circuits”, Automation and Remote Control, vol. 42, No. 3, Part 2, March 1981, 3–10Google Scholar
  11. 11.
    Wakerly, J.: “Error detecting codes, self-checking circuits and applications”, North-Holland, New York, 1977Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Peter Böhlau
    • 1
  1. 1.Max-Planck-Society, Fault Tolerant Computing GroupUniversity of PotsdamPotsdamGermany

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