Abstract
This paper presents a hierarchical test analysis for testing VLSI circuits using random patterns. Circuit components and signals are represented at the register transfer level (RTL). Test analysis of circuit components is a two-step process: first, the test length of stand alone components is estimated with a high detection quality and secondly, the test length of each component in the circuit is computed using the transparency properties of the other components.
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© 1994 Springer-Verlag Berlin Heidelberg
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Masseboeuf, G., Pulou, J., Rainard, J.L. (1994). Hierarchical test analysis of VLSI circuits for random BIST. In: Echtle, K., Hammer, D., Powell, D. (eds) Dependable Computing — EDCC-1. EDCC 1994. Lecture Notes in Computer Science, vol 852. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58426-9_136
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DOI: https://doi.org/10.1007/3-540-58426-9_136
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