Skip to main content

Test generation for digital systems based on alternative graphs

  • Session 4: Hardware testing
  • Conference paper
  • First Online:
Dependable Computing — EDCC-1 (EDCC 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 852))

Included in the following conference series:

  • 145 Accesses

Abstract

A new approach based on using alternative graphs (AG) to create tools for computer aided test pattern design for digital systems is proposed. Different representation levels of digital systems (behavioral, procedural, functional, logical and topological ones) are supported by uniform test design tools based on the same AG-formalism. Instead of using different libraries of component models for solving different test design tasks (fault analysis, test synthesis, multivalued simulation, testability analysis), only a single library of AGs will be used, which reduces the cost of creating and updating component libraries. Aoverview of the model and methods is given and a description of a system for automated test program generation is described.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Abadir M.S., Reghbati H.K. Functional specification and testing of logic circuits. Comp. I Math. with Appls. Vol. 11, No.12, pp. 1143–1153., 1985.

    Article  Google Scholar 

  2. Abramovici M., Breuer M.A. Multiple fault diagnosis in combinational circuits based on an effect-cause analysis. IEEE Trans. Comp., vol. C-29, June, 1980, pp. 451–460.

    Google Scholar 

  3. Akers S.B. 1978). Binary decision diagrams. IEEE Trans. on Computers, Vol. 27, pp. 509–516.

    Google Scholar 

  4. Anirudhan P.N., Menon P.R. Symbolic test generation for hierarchically modeled digital systems. 1989 International Test Conference, pp.461–469.

    Google Scholar 

  5. Beenker F.P.M. et al. Macro testing: Unifying IC and board test. IEEE Design and test of computers. Dec. 1986, pp.26–32.

    Google Scholar 

  6. Calhoun J.D., Brglez F. A framework and method for hierarchical test generation. IEEE International Test Conference, 1989, pp.480–490.

    Google Scholar 

  7. Chandra S.J., Patel J.H. A hierarchical approach to test vector generation. ACM/IEEE 24th Design Automation Conf., June 1987, pp.495–501.

    Google Scholar 

  8. Cheng K.-T., Jou J.-Y. Functional test generation for finite state machines. IEEE International Test Conference, 1990, pp.162–168.

    Google Scholar 

  9. Ghosh A., Chakraborty T.J. On behavior fault modeling for digital designs. J. of Electronic Testing. Theory and Applications, 2, 135–151 (1991).

    Google Scholar 

  10. Giambiasi N. et. al. Test pattern generation for behavioral descriptions in VHDL. Proc. of the VHDL conference, Stockholm, 1991, pp.228–234.

    Google Scholar 

  11. Gupta A.G., Armstrong J.R. Functional fault modeling and simulation for VLSI devices. ACM/IEEE 22nd DAC, 1985, pp.720–726.

    Google Scholar 

  12. Kobayashi K. Functional test data generation for hardware design verification. 1987 IEEE International Test Conferation, pp.547–552.

    Google Scholar 

  13. Krishnamurthy B. Hierarchical test generation: Can AI help? IEEE International Test Conference, Sept. 1987, pp.694–700.

    Google Scholar 

  14. Kuchcinski K. Towards automatic test pattern generation for VHDL description. Proc. of the VHDL conference, Stockholm. 1991.

    Google Scholar 

  15. Kunda R.P., Abraham J.A., Rathi B.D. Speedup of test generation using high-level primitive. ACM/IEEE 27th DAC, pp.580–586, June 1990.

    Google Scholar 

  16. Lee J., Patel J.H. An architectural level test generator for a hierarchical design environment. 21th Int.Symp. on FTC, June, 1991, pp.44–51.

    Google Scholar 

  17. Leenstra J., Spaanenburg L. Hierarchical test assembly for macro based VLSI design. 1990 International Test Conference, pp.520–529.

    Google Scholar 

  18. Lin T., Su S.Y.H. VLSI functional test pattern generation — a design and implementation. 1985 International Test Conference, pp.922–929.

    Google Scholar 

  19. Murray B.T., Hayes J.P. Hierarchical test generation using precomputed tests for modules. IEEE 1988 International Test Conference. pp.221–229.

    Google Scholar 

  20. Murray B.T., Hayes J.P. Test propagation through modules and circuits. 1991 International Test Conference, pp.748–757.

    Google Scholar 

  21. Sarfert T.M., Markgraf R., Trischler E., Schulz M.H. Hierarchical test generation based on high-level primitives. IEEE 1989 ITC, pp.470–479.

    Google Scholar 

  22. Saucier G., Bellon C. CADOC: A system for computer aided functional test. IEEE 1984 International Test Conference, pp.680–687.

    Google Scholar 

  23. Saucier G., Crastes de Paulet M., Tiar F. Functional test of ASICs and Boards. F.Lombardi and M.Sami (eds.). Testing and Diagnosis of VLSI and ULSI. 273–286. 1988 by Kluwer Academic Publishers.

    Google Scholar 

  24. Shen L., Su S.Y.H. A functional testing method for microprocessors. IEEE Trans. on Computers, Oct. 1988, pp. 1288–1293.

    Google Scholar 

  25. Su S.Y.H., Lin T. (1984). Functional testing techniques for digital LSI/VLSI systems. ACM/IEEE 21st DAC, 1984, pp.517–528.

    Google Scholar 

  26. Thatte S.M., Abraham I.A. (1980). Test generation for microprocessors. IEEE Trans. on Computers, Vol. 29. pp. 429–441.

    Google Scholar 

  27. Ubar R. Test generation for digital circuits using alternative graphs. Proc. of Tallinn Technical University, Estonia, No.409, pp.75–81 (in Russian).

    Google Scholar 

  28. Ubar R. Vektorielle alternative Graphen und Fehlerdiagnose für digitale Systeme. Nachrichtentechnik/Elektronik (Germany) 31(1981) H.I. s. 25–28.

    Google Scholar 

  29. Ubar R. Test pattern generation for digital systems on the vector AG-model. 13th Int.Conf.on Fault Tolerant Computing, Milano,Italy,1983, pp.347–351.

    Google Scholar 

  30. Ubar R. Alternative graphs and technical diagnosis of digital devices. Electronic technique. (USSR) Vol.8. No.5 (132). pp.33–57 (in Russian).

    Google Scholar 

  31. Ubar R., Dushina J., Zaugarow S., Krupnova L., Storozhew S. (1993). FTGEN — A system for functional test generation. Proc. of the Int. Conf. CAD 93. Yalta, May 4–13. 1993, pp. 123–125.

    Google Scholar 

  32. Ward P.C., Armstrong J.R. (1990). Behavioral fault simulation in VHDL ACM/IEEE 27th Design Automation Conference, 1990, pp.587–593.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Klaus Echtle Dieter Hammer David Powell

Rights and permissions

Reprints and permissions

Copyright information

© 1994 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Ubar, R. (1994). Test generation for digital systems based on alternative graphs. In: Echtle, K., Hammer, D., Powell, D. (eds) Dependable Computing — EDCC-1. EDCC 1994. Lecture Notes in Computer Science, vol 852. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58426-9_129

Download citation

  • DOI: https://doi.org/10.1007/3-540-58426-9_129

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58426-1

  • Online ISBN: 978-3-540-48785-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics