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Meaningful benchmarks for logic optimization of table-lookup FPGAs

  • Steven H. Kelem
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 849)

Abstract

This paper discusses benchmarks for optimization to table-lookup FPGAs. We discuss a scientific method for systematically generating a set of benchmarks for measuring the effectiveness of a synthesis tool/algorithm for a particular FPGA architecture. The benchmarks have the useful properties of being generated easily, having an a priori, known best result, covering all the possible configurations of a lookup table, and yielding a simple metric. This metric can be used to compare different synthesis tools/algorithms for their efficiency in mapping to a given FPGA architecture. This is in contrast to the ad hoc sets of benchmarks, for which it is difficult to compare results of different optimization tools/algorithms.

Keywords

Boolean Function Lookup Table Truth Table Generate Test Case Logic Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Karen A. Bartlett, et al.: Multilevel Logic Minimization Using Implicit Don't Cares. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 7(6): 723–740, June 1988.Google Scholar
  2. 2.
    Stephen D. Brown, et al.: Field-Programmable Gate Arrays. Kluwer Academic Publishers, Engineering and Computer Science Series. Boston, 1992.Google Scholar
  3. 3.
    Steve Trimberger: A Small, Complete Mapping Library for Lookup-Table-Based FPGAs. In the 2nd International Workshop on Field-Programmable Logic and Applications. IFIP Working Groups 10.2 and 10.5, August 1992Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Steven H. Kelem
    • 1
  1. 1.Xilinx, Inc.USA

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