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ZAREPTA: A zero lead-time, all reconfigurable system for emulation, prototyping and testing of ASICs

  • Tormod Njølstad
  • Johnny Pihl
  • Jørn Hofstad
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 849)

Abstract

Primarily, our ZAREPTA system addresses the need for a low-cost static ASIC tester. By utilizing reconfigurable FPGA technology, the ZAREPTA's total functionality (and 400 DUT pins) can be configured, controlled and monitored by PC software. The main principles of the tester, the block diagram, the software, and the FPGA designs will be explained. However, as a spin-off, the ZAREPTA system may also be used for emulation and fast prototyping of small ASICs. Recently, the ZAREPTA system has been extended with 4 FPIDs, to provide programmable interconnect between the 13 Xilinx XC4005 of ZAREPTA. Bit-serial ASIC architectures with at most 120 external signal pins and 20000 gates may be emulated.

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References

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Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Tormod Njølstad
    • 1
  • Johnny Pihl
    • 1
  • Jørn Hofstad
    • 1
  1. 1.The Norwegian Institute of Technology Faculty of Electrical Engineering & Computer ScienceUniversity of TrondheimTrondheim-NTHNorway

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