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Constraint-based hierarchical placement of parallel programs

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Field-Programmable Logic Architectures, Synthesis and Applications (FPL 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 849))

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Abstract

This paper continues our investigation into the feasibility of exploiting the structure of a parallel program to guide its hardware implementation. We review previous work, and present our new approach to the problem based upon placing netlists hierarchically. It is found that appropriate constraints can be derived from the source code in a straight-forward way, and this information can be used to guide the subsequent placement routines. Comparisons with traditional placement procedures based on simulated annealing are given.

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References

  1. Page, I. and Luk, W.: Compiling occam into FPGAs, in FPGAs, W. Moore and W. Luk, Eds. Abingdon EE&CS Books, pp. 271–283, 1991.

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  2. Luk, W., Ferguson D. and Page, I.: Structured hardware compilation of parallel programs, in More FPGAs, W. Moore and W. Luk, Eds. Abingdon EE&CS Books, pp. 213–224, 1994.

    Google Scholar 

  3. van Laarhoven, P.J.M., Aarts, E.H.L. and Liu, C.L.: Simulated annealing in circuit layout. Nieuw Archief VoorWiskunde, 9(1), pp. 13–39, 1990.

    Google Scholar 

  4. Luk, W.: Systematic serialisation of array-based architectures. Integration, the VLSI Journal, 14(3), pp. 333–360.

    Google Scholar 

  5. Raman S., Liu C.L. and Jones, L.G.: Timing-based placement for an FPGA design environment, in More FPGAs, W. Moore and W. Luk, Eds. Abingdon EE&CS Books, pp. 213–224, 1994.

    Google Scholar 

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Author information

Authors and Affiliations

  1. Programming Research Group, Oxford University Computing Laboratory, Wolfson Building, Parks Road, OX1 3QD, Oxford, UK

    Mat Newman, Wayne Luk & Ian Page

Authors
  1. Mat Newman
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  2. Wayne Luk
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  3. Ian Page
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Editor information

Reiner W. Hartenstein Michal Z. Servít

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© 1994 Springer-Verlag Berlin Heidelberg

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Newman, M., Luk, W., Page, I. (1994). Constraint-based hierarchical placement of parallel programs. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_92

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  • DOI: https://doi.org/10.1007/3-540-58419-6_92

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58419-3

  • Online ISBN: 978-3-540-48783-8

  • eBook Packages: Springer Book Archive

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