A fast FPGA implementation of a general purpose neuron
The implementation of larger digital neural networks has not been possible due to the real-estate requirements of single neurons. We present an expandable digital architecture which allows fast and spaceefficient computation of the sum of weighted inputs, providing an efficient implementation base for large neural networks. The actual digital circuitry is simple and highly regular, thus allowing very efficient space usage of fine grained FPGAs. We take advantage of the re-programmability of the devices to automatically generate new custom hardware for each topology of the neural network.
KeywordsActivation Function Hardware Implementation Shift Register Full Adder Neural Network Design
Unable to display preview. Download preview PDF.
- [CB92]Charles E. Cox and W. Ekkehard Blanz. GANGLION — a fast field-programmable gate array implementation of a connectionist classifier. IEEE Journal of Solid-State Circuits, 27(3):288–299, March 1992.Google Scholar
- [GSM94]Michael Gschwind, Valentina Salapura, and Oliver Maischberger. Space efficient neural net implementation. In Proc. of the Second International ACM/SIGDA Workshop on Field-Programmable Gate Arrays, Berkeley, CA, February 1994. ACM.Google Scholar
- [Hop82]John J. Hopfield. Neural networks and physical systems with emergent collective computational abilities. In Proceedings of the Academy of Sciences USA, volume 79, pages 2554–2558, April 1982.Google Scholar
- [Koh90]Teuvo Kohonen. The self-organizing map. Proceedings of the IEEE, 78(9):1464–1480, September 1990.Google Scholar
- [MOPU93]Michele Marchesi, Gianni Orlando, Francesco Piazza, and Aurelio Uncini. Fast neural networks without multipliers. IEEE Transactions on Neural Networks, 4(1):53–62, January 1993.Google Scholar
- [MS88]Alan F. Murray and Anthony V. W. Smith. Asynchronous VLSI neural networks using pulse-stream arithmetic. IEEE Journal of Solid-State Circuits, 23(3):688–697, March 1988.Google Scholar
- [Sal94]Valentina Salapura. Neural networks using bit stream arithmetic: A space efficient implementation. In Proceedings of the IEEE International Symposium on Circuits and Systems, London, UK, June 1994.Google Scholar
- [vDJST93]Max van Daalen, Peter Jeavons, and John Shawe-Taylor. A stochastic neural architecture that exploits dynamically reconfigurable FPGAs. In IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, April 1993. IEEE CS Press.Google Scholar
- [Xil92]Xilinx. XACT Reference Guide. Xilinx, San Jose, CA, October 1992.Google Scholar
- [Xil93]Xilinx. The Programmable Logic Data Book. Xilinx, San Jose, CA, 1993.Google Scholar