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A fast FPGA implementation of a general purpose neuron

  • Valentina Salapura
  • Michael Gschwind
  • Oliver Maischberger
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 849)

Abstract

The implementation of larger digital neural networks has not been possible due to the real-estate requirements of single neurons. We present an expandable digital architecture which allows fast and spaceefficient computation of the sum of weighted inputs, providing an efficient implementation base for large neural networks. The actual digital circuitry is simple and highly regular, thus allowing very efficient space usage of fine grained FPGAs. We take advantage of the re-programmability of the devices to automatically generate new custom hardware for each topology of the neural network.

Keywords

Activation Function Hardware Implementation Shift Register Full Adder Neural Network Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Valentina Salapura
    • 1
  • Michael Gschwind
    • 1
  • Oliver Maischberger
    • 1
  1. 1.Institut für Technische InformatikTechnische Universität WienWienAustria

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