Achieving the shortest clock period by inserting the minimum amount of delay

  • Shangzhi Sun
  • David H. C. Du
  • Guoliang Xue
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 834)


The performance of a circuit depends on its clock period. The shorter a valid clock period is, the better the performance is. The clock period is tightly related to the difference between the longest propagation delay and the shortest propagation delay from primary inputs to primary outputs. The objective of this paper is to minimize the amount of delay inserted while achieving the shortest clock period.

Inserting delay buffers is done after traditional delay optimization. We propose an optimal algorithm based on a novel linear programming formulation. Our algorithm can also be used to solve similar delay buffer problems.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Shangzhi Sun
    • 1
  • David H. C. Du
    • 1
  • Guoliang Xue
    • 2
  1. 1.Computer Science DepartmentUniversity of MinnesotaUSA
  2. 2.Department of Computer Science and Electrical EngineeringThe University of VermontUSA

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