Achieving the shortest clock period by inserting the minimum amount of delay
The performance of a circuit depends on its clock period. The shorter a valid clock period is, the better the performance is. The clock period is tightly related to the difference between the longest propagation delay and the shortest propagation delay from primary inputs to primary outputs. The objective of this paper is to minimize the amount of delay inserted while achieving the shortest clock period.
Inserting delay buffers is done after traditional delay optimization. We propose an optimal algorithm based on a novel linear programming formulation. Our algorithm can also be used to solve similar delay buffer problems.
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