The parallel hierarchical memory model
Modern computer systems usually have a complex memory system consisting of increasingly larger and slower memory. Traditional computer models like the Random Access Machine (RAM) have no concept of memory hierarchy, making it inappropriate for an accurate complexity analysis of algorithms on these types of architectures.
Aggarwal et al. introduced the Hierarchical Memory Model (HMM). In this model, access to memory location x requires f(x) instead of constant time. In a second paper they proposed an extension of the HMM called the Hierarchical Memory Model with Block Transfer (HMBT), in which a block of consecutive locations can be copied in unit time per element after the initial access latency.
This paper introduces two extensions of the HMBT model: the Parallel Hierarchical Memory Model with Block Transfer (P-HMBT), and the pipelined P-HMBT (PP-HMBT). Both models are intended to model memory systems in which data transfers between memory levels may proceed concurrently.
Tight bounds are given for several problems including dot product, matrix transposition and prefix sums. Also, the relationship between the models is examined. It is shown that the HMBT and P-HMBT are both strictly less powerful than the PP-HMBT. It is also shown that the HMBT and P-HMBT are incomparable in strength.
Index termsHierarchical memory data locality algorithms
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