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A scalable bit-sequential SIMD architecture for pattern recognition

  • Martin Neschen
  • Martin Gumm
Poster Session
Part of the Lecture Notes in Computer Science book series (LNCS, volume 817)

Abstract

A scalable SIMD architecture has been developed for the most efficient implementation of binary pattern classification by nearestneighbor algorithms. A two-dimensional M × N array of asynchronous counters, reflecting an inherent two-fold data parallelism of the applications, reduces the data transfer to off-chip memory from \(\mathcal{O}(M \times N)\) to \(\mathcal{O}(M + N)\) which allows a high integration and efficient use of external memory. Here, we present the realization of a VLSI structure, the system architecture, and possible applications including binary kNN and a completely binary version of k-means.

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References

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    R. O. Duda, P. E. Hart, “Pattern Classification and Scene Analysis”, J. Wiley & Sons, New York, 1973Google Scholar
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    T. M. Cover, P. E. Hart, “Nearest neighbor pattern classification”, IEEE Trans. Info. Theory, IT-13, p. 21, 1967CrossRefGoogle Scholar
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    S. P. Lloyd, “Least square quantization in PCM”, IEEE Trans. Inform. Theory, vol. IT-28, no. 2, p. 129Google Scholar
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    M. Gumm, Technical Report, LIX/RT/93/02, LIX, Ecole Polytechnique, PalaiseauGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Martin Neschen
    • 1
  • Martin Gumm
    • 1
  1. 1.Laboratiore d'InformatiqueEcole polytechniquePalaiseau CedexFrance

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