Abstract
We present a state equivalence that is defined with respect to a given CTL formula. Since it does not attempt to preserve all CTL formulas, like bisimulation does, we can expect to compute coarser equivalences. We use this equivalence to manage the size of the transition relations encountered when model checking a system of interacting FSMs. Specifically, the equivalence is used to reduce the size of each component FSM, so that their product will be smaller. We show how to apply the method, whether an explicit representation is used for the FSMs, or BDDs are used. Also, we show that in some cases our approach can detect if a formula passes or fails, without composing all the component machines. The method is exact and fully automatic, and handles full CTL.
Chapter PDF
References
A. Aziz and R. K. Brayton. Verifying interacting finite state machines. Technical Report UCB/ERL M93/52, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, July 1993.
A. Aziz, T. R. Shiple, V. Singhal, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. Formula-dependent equivalence for compositional CTL model checking. Technical report, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, 1994.
A. Bouajjani, J.-C. Fernandez, N. Halbwachs, P. Raymond, and C. Ratel. Minimal state graph generation. Science of Computer Programming, 18(3):247–271, 1992.
M. C. Browne, E. M. Clarke, and O. Grumberg. Characterizing Kripke structures in temporal logic. Technical Report CS 87-104, Department of Computer Science, Carnegie Mellon University, 1987.
M. Chiodo, T. R. Shiple, A. L. Sangiovanni-Vincentelli, and R. K. Brayton. Automatic compositional minimization in CTL model checking. In Proc. Int'l Conf. on Computer-Aided Design, pages 172–178, Nov. 1992.
E. M. Clarke, E. A. Emerson, and A. P. Sistla. Automatic verification of finite-state concurrent systems using temporal logic specifications. ACM Trans. on Programming Languages and Systems, 8(2):244–263, Apr. 1986.
E. M. Clarke, D. E. Long, and K. L. McMillan. Compositional model checking. In 4th Annual Symposium on Logic in Computer Science, Asilomar, CA, June 1989.
O. Coudert, C. Berthet, and J. C. Madre. Verification of synchronous sequential machines based on symbolic execution. In J. Sifakis, editor, Proceedings of the Workshop on Automatic Verification Methods for Finite State Systems, volume 407 of Lecture Notes in Computer Science, pages 365–373. Springer-Verlag, June 1989.
D. Dams, O. Grumberg, and R. Gerth. Generation of reduced models for checking fragments of CTL. In C. Courcoubetis, editor, Proceedings of the Conference on Computer-Aided Verification, volume 697 of Lecture Notes in Computer Science, pages 479–490. Springer-Verlag, June 1993.
E. A. Emerson. Temporal and modal logic. In J. van Leeuwen, editor, Handbook of Theoretical Computer Science, pages 995–1072. Elsevier Science Publishers B.V., 1990.
O. Grumberg and D. E. Long. Model checking and modular verification. In J. C. M. Baeten and J. F. Groote, editors, CONCUR '91, International Conference on Concurrency Theory, volume 527 of Lecture Notes in Computer Science. Springer-Verlag, Aug. 1991.
R. Milner. Communication and Concurrency. Prentice Hall, New York, 1989.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1994 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Aziz, A., Shiple, T.R., Singhal, V., Sangiovanni-Vincentelli, A.L. (1994). Formula-dependent equivalence for compositional CTL model checking. In: Dill, D.L. (eds) Computer Aided Verification. CAV 1994. Lecture Notes in Computer Science, vol 818. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58179-0_65
Download citation
DOI: https://doi.org/10.1007/3-540-58179-0_65
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-58179-6
Online ISBN: 978-3-540-48469-1
eBook Packages: Springer Book Archive