Abstract
Symbolic trajectory evaluation shows much promise as a method for verifying large scale VLSI designs with a high degree of automation. However, to verify today's designs, a method for composing partial verification results is needed. Consequently, we have proven a number of inference rules for the composition of symbolic trajectory evaluation results and developed a specialised theorem prover designed specifically for combining verification results based on trajectory evaluation. In the paper we discuss the underlying inference rules of the prover as well as more practical issues regarding the user interface. We conclude with an example in which we verify a design that could not have been verified directly. In particular, the complete verification of a 64 bit multiplier takes under 15 minutes on a Sparc 10/51 machine.
This research was supported by operating grant OGPO 109688 from the Natural Sciences Research Council of Canada, a fellowship from the Advanced Systems Institute, and by research contract 92-DJ-295 from the Semiconductor Research Corporation.
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© 1994 Springer-Verlag Berlin Heidelberg
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Hazelhurst, S., Seger, CJ.H. (1994). Composing symbolic trajectory evaluation results. In: Dill, D.L. (eds) Computer Aided Verification. CAV 1994. Lecture Notes in Computer Science, vol 818. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58179-0_61
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DOI: https://doi.org/10.1007/3-540-58179-0_61
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