Methodology and system for practical formal verification of reactive hardware

  • Ilan Beer
  • Shoham Ben-David
  • Daniel Geist
  • Raanan Gewirtzman
  • Michael Yoeli
Part of the Lecture Notes in Computer Science book series (LNCS, volume 818)


Making formal verification a practicality in industrial environments is still difficult. The capacity of most verification tools is too small, their integration in a design process is difficult and the methodology that should guide their usage is unclear.

This paper describes a step-by-step methodology which was developed for the practical application of formal verification. The methodology was successfully realized in a production environment of hardware design. The realization involved the development of a system consisting of several tools, while using the SMV [McM93] verification tool as the system core.

This system was used in the verification of eight designs. We specifically elaborate on the verification of a bus-bridge design, which was particularly successful in uncovering and eliminating many hardware design errors.


  1. [Bee92]
    I. Beer, “Formal Verification of Hardware”, M.Sc. Thesis, EE Department, Technion, 1992 (in Hebrew).Google Scholar
  2. [Bry86]
    R.E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation”, IEEE Trans. Computers, Vol. C-35, August 1986.Google Scholar
  3. [CE81]
    E.M. Clarke and E.A. Emerson, “Design and Synthesis of Synchronization Skeletons using Branching Time Temporal Logic”, in: Proceedings of the Workshop on Logic of Programs, LNCS 131, 1981. Temporal Logic Specifications: A Practical Approach”, Tenth ACM Symposium on Principles of Programming Languages, Austin, Texas, 1983.Google Scholar
  4. [CES83]
    E.M. Clarke, E.A. Emerson and A.P. Sistla, “Automatic Verification of Finite-State Concurrent Systems using Temporal Logic Specifications: A Practical Approach”, Tenth ACM Symposium on Principles of Programming Languages, Austin, Texas, 1983.Google Scholar
  5. [Cli73]
    M. Clint, “Program Proving: Coroutines”, Acta informatica, 2(1), 50–63, 1973.CrossRefGoogle Scholar
  6. [Eme89]
    E.A. Emerson, “Temporal and Modal Logic”, in: Handbook of Theoretical Computer Science, J. van Leeuwen, ed., North-Holland, 1989.Google Scholar
  7. [GB94]
    D. Geist and I. Beer, “Efficient Model Checking by Automated Ordering of Transition Relation Partitions”, submitted for publication, 1994.Google Scholar
  8. [GL91]
    O. Grumberg and D.E. Long, “Model Checking and Modular Verification”, in: LNCS 527, 1991.Google Scholar
  9. [Kur87]
    R.P. Kurshan, “Reducibility in Analysis of Coordination”, in: LNCS 103, 1987.Google Scholar
  10. [Lon93]
    D.E. Long, “Model Checking, Abstraction and Compositional Verification”, Ph.D. Thesis, CMU, 1993.Google Scholar
  11. [McM93]
    K.L. McMillan, “Symbolic Model Checking”, Kluwer Academic Publishers, 1993.Google Scholar
  12. [MP91]
    Z. Manna and A. Pnueli, “The Temporal Logic of Reactive and Concurrent Systems; Specification”, Springer-Verlag, 1991.Google Scholar
  13. [PCI93]
    “PCI Local Bus Specification, Revision 2.0”, PCI Special Interest Group, 1993.Google Scholar
  14. [Pnu86]
    A. Pnueli, “Applications of Temporal Logic to the Specification and Verification of Recative Systems: A Survey of Current Trends”, in: Current Trends in Concurrency, Bakker et al., eds., LNCS 224, 1986.Google Scholar
  15. [SG90]
    G. Shurek and O. Grumberg, “The modular Framework of Computer-Aided Verification: Motivation, Solutions and Evaluation Criteria”, CAV90.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Ilan Beer
    • 1
  • Shoham Ben-David
    • 1
  • Daniel Geist
    • 1
  • Raanan Gewirtzman
    • 1
  • Michael Yoeli
    • 1
  1. 1.IBM Science & TechnologyHaifaIsrael

Personalised recommendations