Optimisations for the memory hierarchy of a Singular Value Decomposition algorithm implemented on the MIMD architecture

  • Adam Czezowski
  • Peter Strazdins
Numerical Algorithms for Engineering
Part of the Lecture Notes in Computer Science book series (LNCS, volume 797)


This paper shows several optimisations to the Hestenes parallel algorithm for Singular Value Decomposition (SVD). The central principle in all of the optimisations presented herein is to increase the number of columns being held in each level of the parallel memory hierarchy. The algorithm was implemented on the Fujitsu's AP1000 Array Multiprocessor, but all optimisations described can be easily applied to any MIMD architecture with mesh or hypercube topology, and all but one can be applied to register-cache uniprocessors also.


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    Czezowski, A., Strazdins, P.: Ways of enhancing performance of a Singular Value Decomposition Algorithm on the AP1000 Array Multiprocessor. Transputer and Occam Engineering Series 31 (1993) 83–88 (ISSN:0925-4986)Google Scholar
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    Czezowski, A., Strazdins, P.: Optimisations for the memory hierarchy of a Singular Value Decomposition Algorithm implemented on the MIMD Architecture. ANU, Department of Computer Science Technical Report TR-CS-94-03 (1994)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Adam Czezowski
    • 1
  • Peter Strazdins
    • 1
  1. 1.Department of Computer ScienceAustralian National UniversityCanberra

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