Advertisement

A finite field arithmetic unit VLSI chip

  • Germain Drolet
Coding and Cryptography
Part of the Lecture Notes in Computer Science book series (LNCS, volume 793)

Abstract

This paper presents a circuit operating on fields F2 [X] /〈f(X)〉 where f(X) is a binary irreducible polynomial of degree m ≥ 2, and F2=GF(2). This circuit is able to perform back to back multiplications and inversions for any such f(X) and any value of m within a specified range, m being possibly large. It is assumed that the elements of the field are expressed as polynomials in X of degree less than m (polynomial basis). The circuit consists mainly of a Serial Input-Serial Output multiplier which is similar to the one published by Yeh, Reed, Truong in 1984. An element of the field is inverted by raising it to the power 2 m — 2, and so the outputs of the multiplier are fed back into its inputs. Even though the circuit can operate on any size of field within the specified range, it is better suited for large fields; circuitry achieving better performance can be designed for small fields (Parallel Input-Parallel Output).

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    K. Araki, I. Fujita, M. Morisue, ”Fast Inverter over Finite Filed Based on Euclid's Algorithm”, Trans. 1EICE, vol. E 72, pp 1230–1234, Nov 1989.Google Scholar
  2. 2.
    L. Childs, A Concrete Introduction to Higher Algebra, Undergraduate Text in Mathematics, Springer-Verlag, New-York, 1979.Google Scholar
  3. 3.
    M. Diab, ”Systolic Architectures for Multiplication over Finite Field GF(2m)”, Applied Algebra, Algebraic Algorithms, and Error Correcting Codes, Proceedings of the 8th International Conference, AAECC-8, Tokyo, Japan, August 1990, Springer-Verlag, pp 329–340.Google Scholar
  4. 4.
    B.K. Green, Design of a Single-Chip Universal Reed-Solomon Decoder, Master's Thesis presented to the Dept. of Elec. and Comp. Eng., Royal Military College, Kingston, Ontario, May 1992.Google Scholar
  5. 5.
    M.A. Hasan, V.K. Bhargava, ”Bit-Serial Systolic Divider and Multiplier for GF(2m)”, IEEE Trans. Comput., vol C-41, no 8, pp 972–980, Aug 1992.MathSciNetGoogle Scholar
  6. 6.
    T.S. Hungerford, Algebra, Graduate Text in Mathematics 73, Springer-Verlag, New-York, 1984.Google Scholar
  7. 7.
    M. Kovac, N. Ranganathan, M. Varanasi, ”SIGMA: A VLSI Systolic Array Implementation of a Galois Field GF(2m) Based Multiplication and Division Algorithm”, IEEE Trans. on VLSI Systems, vol 1, no 1, pp 22–30, Mar 1993.Google Scholar
  8. 8.
    P.A. Scott, S.E. Tavares, L.E. Peppard, ”AS Fast VLSI Multiplier for GF(2m)”, IEEE J. Selected Areas Commun, vol 4, no 1, pp 62–66, Jan 1986.Google Scholar
  9. 9.
    Y.R. Shayan, T. Le-Ngoc, V.K. Bhargava, ”A Versatile Time-Domain Reed-Solomon Decoder”, IEEE J Selected Areas Commun, vol 8, no 8, pp 1535–1542, Oct 1990.Google Scholar
  10. 10.
    C.C. Wang, T.K. Truong, H.M. Shao, L.J. Deutsch, J.K. Omura, I.S. Reed, ”VLSI Architecture for Computing Multiplications and Inverses in GF(2m)”, IEEE Trans. Comput., vol C-34, no 8, pp 709–717, Aug 1985.PubMedGoogle Scholar
  11. 11.
    C.S. Yeh, I.S. Reed and T.K. Truong, “Systolic Multipliers for Finite Fields GF(2m)”, IEEE Trans. Comput., vol C-33, no 4, pp 357–360, Apr 1984.Google Scholar
  12. 12.
    B.B. Zhou, ”A new Bit-serial Systolic Multiplier over GF(2m)”, IEEE Trans. Comput., vol C-37, no 6, pp 749–751, June 1988.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Germain Drolet
    • 1
  1. 1.Dept. of Electrical & Computer EngineeringRoyal Military CollegeKingston

Personalised recommendations