A finite field arithmetic unit VLSI chip
This paper presents a circuit operating on fields F2 [X] /〈f(X)〉 where f(X) is a binary irreducible polynomial of degree m ≥ 2, and F2=GF(2). This circuit is able to perform back to back multiplications and inversions for any such f(X) and any value of m within a specified range, m being possibly large. It is assumed that the elements of the field are expressed as polynomials in X of degree less than m (polynomial basis). The circuit consists mainly of a Serial Input-Serial Output multiplier which is similar to the one published by Yeh, Reed, Truong in 1984. An element of the field is inverted by raising it to the power 2 m — 2, and so the outputs of the multiplier are fed back into its inputs. Even though the circuit can operate on any size of field within the specified range, it is better suited for large fields; circuitry achieving better performance can be designed for small fields (Parallel Input-Parallel Output).
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