FSM shift register realization for improved testability

  • Thomas Mueller-Wipperfuerth
  • Josef Scharinger
  • Franz Pichler
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 763)


An approach for the FSM state assignment problem based on an enhanced algorithm for shift register realizations is presented. A FSM is transformed into a generalized shift register structure, where memory elements are put together to one or more shift registers. The proposed procedure considers a final scan path architecture of FSM memory cells already during state assignment, reducing the hardware overhead for testability purposes by exploiting special optimization potentials. Theoretically founded criteria are used to cancel the computation at an early stage if no fruitful shiftregister realization is possible. Experimental results for two-level and multi-level implementations are given for MCNC benchmark machines.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Thomas Mueller-Wipperfuerth
    • 1
  • Josef Scharinger
    • 1
  • Franz Pichler
    • 1
  1. 1.Johannes Kepler University LinzAustria

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