On reconfigurability of VLSI linear arrays

  • Roberte De Prisco
  • Angelo Monti
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 709)


Fault tolerance through the incorporation of redundancy and reconfiguration is quite common. In a redundant linear array of processing elements, k redundant links of fixed lengths are provided to each element of the array in addition to the regular links connecting neighboring processors. The redundant links may be activated to bypass faulty elements. The number and the distribution of faults can have severe impact on the effectiveness of such a method. In this paper we study the problem of deciding whether a pattern of n blocks of faults is catastrophic for a redundant array. We prove that, for arrays provided of bidirectional links, the problem requires time O(kn). In the unidirectional case we propose an algorithm whose complexity is O(n) when the array has only one redundant link, and O(kn log k) otherwise. When the pattern is not catastrophic we are interested to obtain a reconfiguration set and, in particular, an optimal reconfiguration set (i.e. one with maximal number of working elements). We prove that such a problem is NP-hard, when the links are bidirectional. For the unidirectional case, instead, we present an algorithm of complexity O(kng), where g is the length of the longest link.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    R. De Prisco and A. De Santis “Catastrophic faults in reconfigurable VLSI linear arrays”, Preprint 1993.Google Scholar
  2. 2.
    M. Garey, and D. Johnson, “Computers and Intractability”, Freeman, New York, 1979.Google Scholar
  3. 3.
    E. Horowitz, and S. Sahni, “Fundamentals of computer algorithms”, Computer Science Press, 1978.Google Scholar
  4. 4.
    A. Nayak, “On reconfigurability of some regular architectures”, Ph.D Thesis, Dept. System and Computer Engineering, Carleton University, Ottawa, Canada, 1991.Google Scholar
  5. 5.
    A. Nayak and N. Santoro, “Bounds on performance of VLSI processor arrays”, in 5th Int'l Parallel Processing Symposium, Anaheim, California, May 1991.Google Scholar
  6. 6.
    A. Nayak, N. Santoro, and R. Tan, “Fault-intolerance of reconfigurable systolic arrays”, In Proc. 20th Int. Symp. on Fault Tolerant Computing, FTCS'20, pp. 202–209, 1990.Google Scholar
  7. 7.
    L. Pagli and G. Pucci, “Reliability analysis of redundant VLSI arrays”, Preprint 1992.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Roberte De Prisco
    • 1
  • Angelo Monti
    • 2
  1. 1.Department of Computer ScienceColumbia UniversityNew York
  2. 2.Dipartimento di InformaticaUniversitá di PisaPisaItaly

Personalised recommendations