FPGA implementation of systolic sequence alignment
This paper describes an implementation of a novel systolic array for sequence alignment on the SPLASH reconfigurable logic array. The systolic array operates in two phases. In the first phase, a sequence comparison array due to Lopresti  is used to compute a matrix of distances which is stored in local RAM. In the second phase, the stored distances are used by the alignment array to produce a binary encoding of the sequence alignment. Preliminary benchmarks show that the SPLASH implementation performs several orders of magnitude faster than implementation on supercomputers.
Unable to display preview. Download preview PDF.
- R. J. Lipton and D. P. Lopresti, “A Systolic Array for Rapid String Comparison,” in 1985 Chapel Hill Conference on VLSI, H. Fuchs, Ed. Rockville, MD: Computer Science Press, pp. 363–376, 1985.Google Scholar
- D. P. Lopresti, “Rapid Implementation of a Genetic Sequence Comparator Using Field-Programmable Logic Arrays,” presented at Advanced Research in VLSI Conference, Santa Cruz, March 1991, Invited paper.Google Scholar
- B. A. Shapiro, “An Algorithm for Comparing Multiple RNA Secondary Structures,” Comput. Applic. Biosci., 4, no. 3, pp. 387–393, 1988.Google Scholar
- R. A. Wagner and M. J. Fischer, “The String-to-String Correction Problem,” J. Assn. Comput. Mach., 1, pp. 168–173, 1974.Google Scholar
- Xilinx, Inc., The Programmable Gate Array Data Book. San Jose, CA, 1991.Google Scholar