FPGA implementation of systolic sequence alignment

  • Dzung T. Hoang
  • Daniel P. Lopresti
Rapid Prototyping
Part of the Lecture Notes in Computer Science book series (LNCS, volume 705)


This paper describes an implementation of a novel systolic array for sequence alignment on the SPLASH reconfigurable logic array. The systolic array operates in two phases. In the first phase, a sequence comparison array due to Lopresti [1] is used to compute a matrix of distances which is stored in local RAM. In the second phase, the stored distances are used by the alignment array to produce a binary encoding of the sequence alignment. Preliminary benchmarks show that the SPLASH implementation performs several orders of magnitude faster than implementation on supercomputers.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Dzung T. Hoang
    • 1
  • Daniel P. Lopresti
    • 2
  1. 1.Department of Computer ScienceBrown UniversityProvidenceUSA
  2. 2.Matsushita Information Technology LaboratoryPrincetonUSA

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