Automatic one-hot re-encoding for FPGAs
The most common design migrated from PLDs to FPGAs is a state machine. Because of the wide input gates available in PLDs, fully encoded state machines are usually used. However, in register rich FPGAs with narrower gates, one-hot state machines are usually preferred. This paper describes a logic synthesis algorithm which automatically translates a functional level encoded state machine to an equivalent one-hot machine. The result is that without any manual redesign, a PLD state machine can be optimally re-implemented in an FPGA technology such as Xilinx or Actel.
Unable to display preview. Download preview PDF.
- Alfke, Peter, “Accelerate FPGA Macros with One-hot Approach”, Electronic Design, September 13, 1990.Google Scholar
- “FPGAs are Better for State Machines than PLDs”, FPGA Design Guide, Actel Corporation, August 1991.Google Scholar
- Ashar, P, A. Ghosh, S. Devadas, A. R. Newton, “Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test”, Proc ICCAD 1990, pp 84–87.Google Scholar
- Brayton, R. K, G. D. Hachtel, C. T. McMullen and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluver Academic Publishers, 1985Google Scholar