Advertisement

Skewed-associative caches

  • André Seznec
  • Francois Bodin
Paper Sessions Architectures: Caches
Part of the Lecture Notes in Computer Science book series (LNCS, volume 694)

Abstract

During the past decade, microprocessor peak performance has increased at a tremendous rate using RISC concept, higher and higher clock frequencies and parallel/pipelined instruction issuing. As the gap between the main memory access time and the potential average instruction time is always increasing, it has become very important to improve the behavior of the caches, particularly when no secondary cache is used (i.e on all low cost microprocessor systems). In order to improve cache hit ratios, set-associative caches are used in some of the new superscalar microprocessors.

In this paper, we present a new organization for a multi-bank cache: the skewed-associative cache. Skewed-associative caches have a better behavior than set-associative caches: typically a two-way skewed-associative cache has the hardware complexity of a two-way set-associative cache, yet simulations show that it exhibits approximatively the same hit ratio as a four-way set associative cache of the same size.

Keywords

microprocessors cache set-associative cache skewed-associative cache 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    A. Agarwal, M. Horowitz, J. Hennesy “Cache performance of operating systems and multiprogramming work-loads” ACM Transactions on Computer Systems, Nov. 1988Google Scholar
  2. 2.
    A. Agarwal Analysis of Cache Performance for Operating Systems and Multiprogramming, Kluwer Academic Publishers, 1989Google Scholar
  3. 3.
    T.E. Anderson, H.M. Levy, B.N Bershad, E.D. Lazowska “The interaction of architecture and operating system design” Proceedings of ASPLOS IV, April 1991Google Scholar
  4. 4.
    M.D. Hill, “A case for direct-mapped caches”, IEEE Computer, Dec 1988Google Scholar
  5. 5.
    M.D.Hill, A.J. Smith “Evaluating Associativity in CPU Caches” IEEE Transactions on Computers, Dec. 1989Google Scholar
  6. 6.
    N.P. Jouppi, D.W. Wall “Available instruction-level parallelism for superscalar and superpipelined machines “ Proceedings of ASPLOS III, April 1989Google Scholar
  7. 7.
    N.P. Jouppi, “Improving Direct-Mapped Cache Performance by the addition of a Small Fully-Associative Cache and Prefetch Buffers” Proceedings of the 17th International Symposium on Computer Architecture, June 1990Google Scholar
  8. 8.
    M. Lam, E. Rothberg and M. Wolf, “The Cache Performance and Optimizations of Blocked Algorithms”, Proceedings of ASPLOS IV, April 91Google Scholar
  9. 9.
    J.R.Larus, “Abstract execution: a technique for Efficiently Tracing Programs” Technical Report, Computer Sciences Departement, University of Wisconsin-Madison, May 1990Google Scholar
  10. 10.
    J.C. Mogul, A. Borg “The effect of context switches on cache performance” Proceedings of ASPLOS IV, April 1991Google Scholar
  11. 11.
    A. Seznec, “A case for two-way skewed-associative caches”, Proceedings of the 20th International Symposium on Computer Architecture, May 1993Google Scholar
  12. 12.
    A. J. Smith “A Comparative Study of Set Associative Memory Mapping Algorithms and Their Use for Cache and Main Memory” IEEE Transactions on Sofware Engineering, March 1978Google Scholar
  13. 13.
    A.J. Smith “Cache memories” ACM Computing Surveys, Sept. 1982Google Scholar
  14. 14.
    A.J. Smith “Line (block) size choice for CPU cache memories” IEEE Transactions on Computers, Sept. 1987Google Scholar
  15. 15.
    M.D. Smith, M. Johnson, M.A. Horowitz “Limits on multiple instruction issue” Proceedings of ASPLOS III, April 1989Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • André Seznec
    • 1
  • Francois Bodin
    • 1
  1. 1.IRISARennes CedexFrance

Personalised recommendations