Analysis of the TMS320C40 communication channels using timed Petri Nets
The Texas Instruments' TMS320C40 Digital Signal Processor's communication ports and their associated DMA channels have been modelled using Timed Petri Nets. The Petri Net implementation is discussed, and the performance of the communication ports/DMA channels are evaluated. Analysis of the simulation results indicate that the single DMA bus provides insufficient bandwidth to drive the communication ports at maximum speed. During split mode operation the requirement to exchange the bus token reduces the communication bandwidth.
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- 1.Peterson, J.L., “Petri Nets”, Computing Surveys, Vol. 9, No. 3, pp. 223–252, Sept 1977.Google Scholar
- 2.Adiga, A.K. and Deshpande, S.R., “Evaluation of Effectiveness of Circuit Based and Packet Based Interconnection Networks via Petri Net Models”, Proc. 1987 International Conference on Parallel Processing, pp. 533–541, 1987.Google Scholar
- 3.Texas Instruments Inc., TMS320C4x User's Guide, 1991.Google Scholar
- 4.Dally, W.J. and Song, P., “Design of a Self-Timed VLSI Multicomputer Communication Controller”, Proc. International Conference on Computer Design, pp. 230–234, 1987.Google Scholar
- 5.Marsan, M.A., “Stochastic Petri Nets: An Elementary Introduction”, Advances in Petri Nets, G. Rozenberg (ed), Springer-Verlag, pp. 1–29, 1989.Google Scholar