Hardware design for self organizing feature maps with binary input vectors
A number of applications of self organizing feature maps require a powerful hardware. The algorithm of SOFMs contains multiplications, which need a large chip area for fast implementation in hardware. In this paper a resticted class of self organizing feature maps is investigated. Hardware aspects are the fundamental ideas for the restictions, so that the necessary chip area for each processor element in the map can be much smaller then before and more elements per chip can work in parallel. Binary input vectors, Manhatten Distance and a special treatment of the adaptation factor allow an efficient implementation. A hardware design using this algorithm is presented. VHDL simulations show a performance of 25600 MCPS (Million Connections Per Second) during the recall phase and 1500 MCUPS (Million Connections Updates Per Second) during the learning phase for a 50 by 50 map. A first standard cell layout containing 16 processor elements and full custom designs for the most important parts are presented.
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