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Architectures for self-learning neural network modules

  • T G Clarkson
  • C K Ng
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 686)

Abstract

The pRAM (probabilistic RAM) models the non-linear and stochastic features found in biological neurons. The pRAM is realisable in hardware and the fourth generation VLSI pRAM chip is described here. This chip contains 256 pRAM neurons and learning algorithms are built into the hardware. Several such chips can be connected together to form larger nets.

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References

  1. [1]
    “Hardware realisable models of neural processing”, T G Clarkson, D Gorse and J G Taylor, Proc. 1st IEE Int. Conf. on Artificial Neural Networks, London, 242–246, 1989.Google Scholar
  2. [2]
    “From Wetware to Hardware: Reverse Engineering using Probabilistic RAMs”, Clarkson T G, Gorse D and Taylor J G, Special Issue: “Advances in Digital Neural Networks”, Journal of Intelligent Systems, 4, 11–30, Freund, London, 1992.Google Scholar
  3. [3]
    “Generalisation in Probabilistic RAM Nets”, Clarkson T G, Gorse D and Taylor J G, IEEE Transactions on Neural Networks (in print).Google Scholar
  4. [4]
    “Learning Probabilistic RAM Nets Using VLSI Structures”, Clarkson T G, Gorse D, Taylor J G, Ng C K, IEEE Transactions on Computers, Vol. 41, 12, 1992.Google Scholar
  5. [5]
    “Biologically plausible learning in hardware realisable nets”, T G Clarkson, D Gorse and J G Taylor, Proc. ICANN91 Conf., Helsinki, 195–199, 1991.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • T G Clarkson
    • 1
  • C K Ng
    • 1
  1. 1.Department of Electronic and Electrical Engineering King's College LondonCommunications Research GroupStrandUK

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