A model based approach to the performance analysis of multi-layer networks realised in linear systolic arrays

  • David Naylor
  • Simon Jones
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 686)


An analytical model is presented for assessing the hardware performance of multi-layer neural networks realised in linearly connected systolic arrays. Metrics to assess latency, throughput, and computational and I/O bandwidth during the recall stage are derived and applied in the analysis of a variety of multi-layer structures. The effects of the performance metrics on networks with one and two hidden layers are compared in the paper. It is found that a single hidden layer is beneficial to the computational bandwidth across a wide range of hidden layer dimensions, whereas the throughput rate of networks with two hidden layers is higher than for a single layer, even when more hidden neurons are present.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Kung S Y and Hwang J N, ‘A Unifying Algorithm/Architecture for Artificial Neural Networks', International Conference on Application Specific Signal Processors, pp2505–2508, Edinburgh, Scotland, 23–26 May 1989.Google Scholar
  2. 2.
    S R Jones, K Sammut and J Hunter, ‘Toroidal Neural Network Processor: Architecture, Operation, Performance’ 2nd International Conference on Microelectronics for Neural Networks, pp163–169, Munich, Germany, 16–18 Oct 1991.Google Scholar
  3. 3.
    D J Myers, ‘Digital Implementation of Neural Networks', British Telecom Technology Journal, Vol 10, No 1, PP141–148, January 1992.Google Scholar
  4. 4.
    Kung S Y and Hwang J N, ‘An Algebraic Projection for Optimal Hidden Units Size and Learning Rates in Back Propagation Learning', Proceedings of the IEEE International Conference on Neural Networks, Vol 1, PP363–370, San Diego, 1988.Google Scholar
  5. 5.
    Sietsma J and Dow R J F, ‘Creating Artificial Neural Networks that Generalise', Neural Networks, Vol 4, PP67–79, 1991.Google Scholar
  6. 6.
    Li-Min Fu, ‘Analysis of the Dimensionality of Neural Networks for Pattern Recognition', Pattern Recognition, Vol 23, No 10, pp1131–1140, 1990.Google Scholar
  7. 7.
    Kung S Y and Hwangi J N, ‘Digital VLSI Architectures for Neural Networks', International Symposium on Circuits and Systems, ISCAS 89, Vol 1, pp445–448, 1989.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • David Naylor
    • 1
  • Simon Jones
    • 1
  1. 1.Department of Electronic and Electrical EngineeringLoughborough University of TechnologyLoughborough

Personalised recommendations