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A parallel architecture for a VLSI-hardware-realization of a numerical stable variant of the Simplex-Method

  • Bernd Schütz
  • Reinhard Rauscher
Posters
Part of the Lecture Notes in Computer Science book series (LNCS, volume 634)

Abstract

A hardware realization of the Simplex Method is represented. We customised the algorithm regarding numerical stability (arithmetics) and hardware proximity. The resulting hardware (VLSI custom chips, FPUs, RAM) of our accelerator is based on a parallel architecture with up to eight processing units.

References

  1. [1]
    European Silicon Structures Ltd. SOLO 2030 Release 3.1 Reference Manual. Berkshire, 1991.Google Scholar
  2. [2]
    Karl Heinz Borgward. The Simplex Method — A Probabilistic Analysis. Springer-Verlag, Berlin, 1987.Google Scholar
  3. [3]
    A. Klindworth. Entwurf, Simulation und Realisierung einer parallelen Rechnerarchitektur für ein revidiertes Simplex-Verfahren. Diploma Thesis, Department of Computer Science, University of Hamburg, 1992Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1992

Authors and Affiliations

  • Bernd Schütz
    • 1
  • Reinhard Rauscher
    • 1
  1. 1.Dept. of Computer ScienceUniversity of HamburgHamburg 54Germany

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