Abstract
A hardware realization of the Simplex Method is represented. We customised the algorithm regarding numerical stability (arithmetics) and hardware proximity. The resulting hardware (VLSI custom chips, FPUs, RAM) of our accelerator is based on a parallel architecture with up to eight processing units.
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References
European Silicon Structures Ltd. SOLO 2030 Release 3.1 Reference Manual. Berkshire, 1991.
Karl Heinz Borgward. The Simplex Method — A Probabilistic Analysis. Springer-Verlag, Berlin, 1987.
A. Klindworth. Entwurf, Simulation und Realisierung einer parallelen Rechnerarchitektur für ein revidiertes Simplex-Verfahren. Diploma Thesis, Department of Computer Science, University of Hamburg, 1992
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© 1992 Springer-Verlag Berlin Heidelberg
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Schütz, B., Rauscher, R. (1992). A parallel architecture for a VLSI-hardware-realization of a numerical stable variant of the Simplex-Method. In: Bougé, L., Cosnard, M., Robert, Y., Trystram, D. (eds) Parallel Processing: CONPAR 92—VAPP V. VAPP CONPAR 1992 1992. Lecture Notes in Computer Science, vol 634. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55895-0_490
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DOI: https://doi.org/10.1007/3-540-55895-0_490
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