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Very high speed vectorial processors using serial multiport memory as data memory

  • A. Mzoughi
  • M. Lalam
  • D. Litaize
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 634)

Abstract

Complex scientific problems involving large volumes of data need a huge computing power. Memory bandwidth remains a key issue in high performance systems. This paper presents an original method of memory organization based on serial multiport memory components which allows simultaneous access to all ports without causing either conflict between them or suspension. The resulting process for information exchange gives a cost effective realization of a data memory for vector processors. The memory bandwidth can be considerably increased in a modular manner, without practical implementation constraints.

Keywords

serial multiport memory memory bandwidth realignment network vector processor 

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References

  1. 1.
    Kenneth E. Batcher, “Design of a Massively Parallel Processor”, pp.104–08, Tutorial Supercomputers design and applications Kai Hwang Computer Society Press, 1984.Google Scholar
  2. 2.
    Burton J. Smith, “Architecture and applications of the Hep Multiprocessor Computer System”, pp. 231–238, Tutorial Supercomputers Design and Applications Kai Hwang Computer Society Press, 1984.Google Scholar
  3. 3.
    Tse-Yun Feng, “A Survey of Interconnection Networks”, pp. 109–124, Tutorial Supercomputer Design and Applications Kai Hwang Computer Society Press, 1984.Google Scholar
  4. 4.
    Kai Hwang and Fayé A. Briggs, “Computer Architecture and Parallel Processing”, pp. 145–320, Mc Graw Hill Book Company, New York, 1984.Google Scholar
  5. 5.
    Supercomputers, Class VI Systems, Hardware and Software, pp. 1–168, Elsevier Science Publishers B.V, North Holland, 1986.Google Scholar
  6. 6.
    Clifford N. Arold, “ Vector Optimisation on the Cyber 205 ”, pp. 179–185, Tutorial Supercomputer Design and Applications Kai Hwang Computer Society Press, 1984.Google Scholar
  7. 7.
    Howard Jay Siegel, “Interconnection Networks for Large Scale Parallel Processing Theories and case Studies ”, pp. 35–173, D.C. Heath and Company, Massachusetts, 1985.Google Scholar
  8. 8.
    RW Hockney and CR Jesshop, “ Parallel Computers: Architecture, Programming and Algorithms ”, 2nd ed., pp. 82–205, Bristol: Adam Hilger, Great Britain, 1988.Google Scholar
  9. 9.
    Duncan H. Lawrie and Chandra R. Vora, “ The Prime Memory System For Array Access” pp. 435–442, IEEE Transactions on Computers, vol C-31, N∘ 5, may 1982.Google Scholar
  10. 10.
    Duncan H. Lawrie, “ Access and Alignment of data in an Array Processor ”, IEEE Transactions Computer, Vol C-24 N∘ 12, pp. 1145–1154, December 1975.Google Scholar
  11. 11.
    De-lei Lee, “Scrambled Storage for Parallel Memory Systems”, Computer Architecture News, Vol. 16, N∘2, pp. 232–239, May 1988.Google Scholar
  12. 12.
    D. Litaize, A. Mzoughi, C. Rochange, P. Sainrat, “Towards a Shared-Memory Massively Parallel Multiprocessor”, The 19th ISCA,Vol. 20, N∘ 2, pp. 70–79, May 1992.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1992

Authors and Affiliations

  • A. Mzoughi
    • 1
  • M. Lalam
    • 1
  • D. Litaize
    • 1
  1. 1.I. R. I. T. /Université Paul SabatierToulouseFrance

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