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Reducing network hardware quantity by employing multi-processor cluster structure in distributed memory parallel processors

  • Naoki Hamanaka
  • Junji Nakagoshi
  • Teruo Tanaka
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 634)

Abstract

This paper describes a cluster structure to reduce the amount of network hardware in distributed memory parallel processors. The expected reduction in the data transfer rate as the number of nodes is reduced is avoided by raising the transfer rate of each path. Calculations for typical application programs show that clustering can reduce the hardware quantity by 40% provided that inner-cluster parallel processing efficiency is sufficiently high.

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References

  1. [1]
    Tanaka, T., Hamanaka, N. and Muramatsu, A., “The MIMD Type Parallel Processing Architecture based on Tagged Data Transfer”, Proceedings of the Parallel Processing Symposium, 1989 (in Japanese).Google Scholar
  2. [2]
    Hanawa, M., Nishimukai, T., Nishii, O., Suzuki, M., Yano, K., Hiraki, M., Shukuri, S. and Nishida, T., “On-Chip Multiple Superscalar Processors with Secondary Cache Memories”, Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computers & Processors, 1991.Google Scholar
  3. [3]
    Hamanaka, N., Tanaka, T. and Muramatsu, A., “Performance Evaluation of a Numerical Calculation Oriented Macro Dataflow Computer”, Dataflow Workshop, 1987 (in Japanese).Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1992

Authors and Affiliations

  • Naoki Hamanaka
    • 1
  • Junji Nakagoshi
    • 1
  • Teruo Tanaka
    • 1
  1. 1.Central Research Lab.Hitachi, Ltd.TokyoJapan

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