Mixed-mode multicomputers with load adaptability

  • M. S. Baig
  • T. A. El-Ghazawi
  • N. A. Alexandridis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 605)


Dynamically reconfigurable mixed-mode computers are those systems that can be configured at run-time into Multiple SIMD and MIMD autonomous submachines. Therefore, they are also known as MSIMD/MIMD computers. In the existing MSIMD/MIMD architectures, the role of a processor to run as either a processing element “PE” or a control unit “CU”, is fixed at design time. It will be shown that such static assignment adversely affects the system's flexibility and performance. This paper introduces an MSIMD/MIMD architecture with dynamic processors assignments. Unlike the existing machines, this architecture dynamically configures/reconfigures each processor to run as either a PE or a CU as needed. A cost-efficient dynamically reconfigurable hardware is provided in order to establish a broadcasting link between any CU and its PEs in an SIMD submachine. It will be shown that the proposed architecture offers significantly better performance/cost ratio than the existing comparables.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    H.J. Siegel et al., “PASM: A partitionable SIMD/MIMD system for image processing and pattern recognition, “IEEE Trans. on Computers, vol. c-30, Dec. 1981, pp. 934–947.Google Scholar
  2. [2]
    M. Sharma et al., “NETRA: An architecture for a large multi-processor vision system, “Parallel Computer Vision, L. Uhr, editor, Academic Press Inc., Florida, 1987.Google Scholar
  3. [3]
    Y.W.Ma & R. Krishnamurti, “The Architecture of REPLICAA Special Purpose Computer System for Active Multi-sensory Perception for 3-dimensional Objects, “Proc. of Int'l Conf. on Parallel Processing, Aug 1984, pp.30–37.Google Scholar
  4. [4]
    Nutt G.J., “Microprocessor Implementation of a Parallel Processor,” 4th Annual Symposium on Computer Architecture, Mar. 1977, pp.147–152.Google Scholar
  5. [5]
    F.A. Briggs et al., “PM4-A reconfigurable multiprocessor system for pattern recognition and image processing, “Proc. of National Computer Conf. 1979, pp.255–265.Google Scholar
  6. [6]
    H.J.Siegel et al., “A survey of interconnection methods for reconfigurable parallel processing systems, “Proc. National Computing Conf., 1979, pp.529–541.Google Scholar
  7. [7]
    Tucker and Robertson, “Architecture and Applications of the Connection Machine,” Computer, vol 21, Aug. 1988, pp. 26–38.CrossRefGoogle Scholar
  8. [8]
    W.D. Hillis, The Connection Machine, Cambridge, MA: The MIT Press, 1989.Google Scholar
  9. [9]
    Shahid H. Bokhari, “On the Mapping Problem, ”IEEE Trans. on Computers, vol c-30, March 1981, pp. 207–214.Google Scholar
  10. [10]
    L.Snyder, “Introduction to the Configurable Highly Parallel Computer, “Computer, Jan. 1982, pp.47–56.Google Scholar
  11. 11]
    W.Lin & C. L. Wu, “Reconfiguration procedures for a Polymorphic and Partitionable Multiprocessor, ” IEEE Trans. on Computers, vol c-35, Oct. 1986, pp. 910–916.Google Scholar
  12. [12]
    H.Li & M. Maresca, “Polymorphic-Torus Network,” IEEE Trans. on Computers, vol 38, Sept. 1989, pp. 1345–1351.CrossRefGoogle Scholar
  13. [13]
    F.Weil et al., “An analysis of fixed-assignment hypercube partitioning,” Int'l Conf.on Parallel Processing, vol. 1, Aug. 1990, pp. 222–225.Google Scholar
  14. [14]
    Tse-yun Feng, “A survey of interconnection networks, “Computer, Dec. 1981, pp.12–27.Google Scholar
  15. [15]
    K.C.Knowlton, “A fast storage allocator,” Commun. ACM, vol.8, Oct. 1965, pp.623–625.CrossRefGoogle Scholar
  16. [16]
    M.S.Chen & K.G. Shin, “Processor Allocation in an N-cube Multiprocessor using Gray Codes,” IEEE Trans. on Computing, vol 36, Dec. 1987, pp. 1396–1407.Google Scholar
  17. [17]
    J.Kim et al., “A top-down processor allocation scheme for hypercube computers,” IEEE Trans. on Parallel and Distributed Systems, vol. 2, Jan. 1991, pp.20–30.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1992

Authors and Affiliations

  • M. S. Baig
    • 1
  • T. A. El-Ghazawi
    • 1
  • N. A. Alexandridis
    • 1
  1. 1.Department of Electrical Engineering and Computer ScienceThe George Washington UniversityWashington, D.C.USA

Personalised recommendations