Multiplication as parallel as possible
Public key encryption/decryption with modulus arithmetic is used in a variety of cryptographic applications. A tough computational problem arises due to the very long integer arithmetic needed. Usually serial-parallel multiplication is employed, which slows down speed to the order of k=log2(n), where n is the modulus. This paper describes a possible implementation of a method using parallel multiplication schemes at the order of log(k) in combination with incomplete modulus reduction. As many partial products as possible are implemented in parallel (As Parallel As Possible, APAP). This leads to a mixture of linear and logarithmic time complexity. This paper describes a hardware solution for the APAP-multiplier with optimized dynamic adder cells without storage elements. Additional available silicon area can be traded against speedup in a smooth way. The underlying method is described and proved in [Posch90]. Using 664 bit long operands, a 40mm2 chip manufactured in 1.2 micron CMOS technology can reach an RSA encryption/decryption rate of 240 kbits/second.
Keywordspublic key cryptosystems cryptography hardware algorithms VLSI parallel multiplier high speed multiplier
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