Abstract
Given a grid based wire layout, the objective of the layer assignment problem we investigate in this paper is to minimize the interconnect delay by taking into account the conductivity of interconnection wires and vias. For MOS circuits with two or more layers for interconnections, the problem is shown to be NP-hard. It remains NP-hard for the case of two layers having the same conductivity (PDW(=)2) and for the case of two layers with extremely different conductivities (PDW(≠) 2). However, PDW(≠)2 can be reduced to a generalized flow problem which gives hope of good approximating heuristics not only for PDW(≠) 2 but also for the general problem. PDW(≠)2 can be solved in polynomial time when the routing grid is sufficiently fine.
Research supported by DFG, SFB124, TP B1/B2, VLSI Entwurfsmethoden und Parallelität.
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© 1992 Springer-Verlag Berlin Heidelberg
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Kaufmann, M., Molitor, P., Vogelgesang, W. (1992). Performance driven k-layer wiring. In: Finkel, A., Jantzen, M. (eds) STACS 92. STACS 1992. Lecture Notes in Computer Science, vol 577. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55210-3_207
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DOI: https://doi.org/10.1007/3-540-55210-3_207
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