This work was partially funded by the French Coordinated Research Program C 3 and by the Esprit BRA project NANA.
This article was processed using the IIEX macro package with LMAMULT style
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
References
P. Borras, D. Clément, Th. Despeyroux, J. Incerpi, G. Kahn, B. Lang, and V. Pascual. CENTAUR: the System. Technical Report 777, INRIA, 1987.
S.N. Cole. Real-time computation by n-dimensional iterative arrays of finite-state machines. IEEE Tr. on Computer, 18(4):349–365, 1969.
C. Dezan, E. Gautrin, H. Leverge, P. Quinton, and Y. Saouter. Synthesis of systolic arrays by equation transformations. In ASAP'91, IEEE, Barcelona, Spain, September 1991.
J.L.A. Van de Snepscheut and J.B. Swenker. On the design of some systolic algorithms. JACM, 36:826–840, 1989.
C. Dezan, H. Le Verge, P. Quinton, and Y. Saouter. The Alpha du Centaur environment. In P. Quinton and Y. Robert, editors, International Workshop Algorithms and Parallel VLSI Architectures II, North-Holland, Bonas, France, June 1991.
S.Y. Kung, K.S. Arun, R.J. Gal-Ezer, and D.V.B. Rao. Wavefront array processor: language, architecture, and applications. IEEE Trans. on Computers, C-31(11):1054–1066, Nov 1982.
R.M. Karp, R.E. Miller, and S. Winograd. The organization of computations for uniform recurrence equations. Journal of the Association for Computing Machinery, 14(3):563–590, July 1967.
H. T. Rung. Why systolic architectures? IEEE Computer, 15(1):37–46 multiprocessors, parallel processing, systolic arrays, VLSI, January 1982.
H. Leverge. Reduction operators in Alpha. Research Report, IRISA, adressirisa, November 1991. to appear.
H. Leverge, C. Mauras, and P. Quinton. A language-oriented approach to the design of systolic chips. In International Workshop on Algorithms and Parallel VLSI Architectures, Pont-à-Mousson, June 1990. To appear in the Journal of VLSI Signal Processing, 1991.
H. Leverge, C. Mauras, and P. Quinton. The ALPHA language and its use for the design of systolic arrays. Journal of VLSI Signal Processing, 3:173–182, 1991.
C.E. Leiserson and J.B. Saxe. Optimizing synchronous systems. In 22th Annual Symp. on Foundations of Computer Science, pages 23–36, IEEE Press, Oct 1981.
D.I. Moldovan. On the analysis and synthesis of VLSI algorithms. IEEE Transactions on Computers, C-31(11), November 1982.
P. Quinton and V. Van Dongen. The mapping of linear recurrence equations on regular arrays. The Journal of VLSI Signal Processing, 1:95–113, 1989. Quinton89c.
S.K. Rao. Regular Iterative Algorithms and their Implementations on Processor Arrays. PhD thesis, Standford University, U.S.A., October 1985.
A. Schrijver. Theory of Linear and Integer Programming. Wiley-Interscience series in Discrete Mathematics, John Wiley and Sons, 1986.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1992 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Le Verge, H., Quinton, P. (1992). The palindrome systolic array revisited. In: Banâtre, J., Le Métayer, D. (eds) Reasearch Directions in High-Level Parallel Programming Languages. HLPPP 1991. Lecture Notes in Computer Science, vol 574. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55160-3_51
Download citation
DOI: https://doi.org/10.1007/3-540-55160-3_51
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-55160-7
Online ISBN: 978-3-540-46762-5
eBook Packages: Springer Book Archive