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Integer multiplication in PARSAC-2 on stock microprocessors

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Book cover Applied Algebra, Algebraic Algorithms and Error-Correcting Codes (AAECC 1991)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 539))

Abstract

We study the practical performance of three algorithms for integer multiplication, “school-book,” Karatsuba, and 3-primes FFT. We compare portable solutions written in C versus non-portable solutions with assembly subroutines, and we examine the influence of CISC versus RISC processor architecture, in particular the NS 32332 versus Sun's SPARC. We also determine the gains from a parallelization on a shared memory Encore Multimax under Mach. Our software environment is PARSAC-2, a multi-threaded, parallel extension of SAC-2.

This material is based upon work supported by the National Science Foundation under Award No. CCR-9009396.

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Author information

Authors and Affiliations

  1. Department of Computer and Information Science, The Ohio State University, 43210-1277, Columbus, OH, USA

    Wolfgang Kuechlin, David Lutz & Nicholas Nevin

Authors
  1. Wolfgang Kuechlin
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  2. David Lutz
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  3. Nicholas Nevin
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Editor information

Harold F. Mattson Teo Mora T. R. N. Rao

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© 1991 Springer-Verlag Berlin Heidelberg

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Kuechlin, W., Lutz, D., Nevin, N. (1991). Integer multiplication in PARSAC-2 on stock microprocessors. In: Mattson, H.F., Mora, T., Rao, T.R.N. (eds) Applied Algebra, Algebraic Algorithms and Error-Correcting Codes. AAECC 1991. Lecture Notes in Computer Science, vol 539. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-54522-0_109

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  • DOI: https://doi.org/10.1007/3-540-54522-0_109

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-54522-4

  • Online ISBN: 978-3-540-38436-6

  • eBook Packages: Springer Book Archive

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