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Reduced labelled transition systems save verification effort

  • Antti Valmari
  • Matthew Clegg
Selected Presentations
Part of the Lecture Notes in Computer Science book series (LNCS, volume 527)

Abstract

A new method for reducing the amount of effort in the verification of Basic Lotos specifications is presented. The method is based on generating a reduced labelled transition system (RLTS) of the specification. The RLTS captures the semantics of the specification in the sense of the semantic theory of CSP but it is typically much smaller than the ordinary labelled transition system (LTS) of the specification. Thus it can replace the LTS in the verification of the equivalence (in CSP sense) of two specifications. The method is demonstrated with a bounded buffer example where an exponential saving of states is achieved.

Keywords

Behaviour Expression Label Transition System Communicate Sequential Process Optimal Simulation Computation Tree Logic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1991

Authors and Affiliations

  • Antti Valmari
    • 1
  • Matthew Clegg
    • 1
  1. 1.Technical Research Centre of Finland Computer Technology LaboratoryOuluFinland

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