A 30 Mbits/s (255,223) reed-solomon decoder
The paper describes the VLSI implementation of a Reed-Solomon Coder-Decoder. This standard cell ASIC has been designed with VLSI Technology CAD tools on a SUN/4 workstation.
The chip includes two 256-byte ROM — table look-up for the inverse of field elements in GF(28) —, one 512-byte RAM (buffer register) and the equivalent of 55 Kgates. The die size is 440 mils × 440 mils and the process used for manufacturing is CMOS 1.0 µ.
The Reed-Solomon code is a (N,N-32) block code of 8-bit symbols capable of correcting up to v symbol errors and ρ symbol erasures provided that 2v+ρ≤32. N assumes values less than or equal to 255 (when N<255 a shortened code is generated).
The data rate achieved by the decoder depends on the dimension K of the code selected and equals K÷256×34 Mbits/s (34 MHz is the maximum frequency corresponding to the industrial worst case). For example the (255,223)RS operates at 30 Mbits/s compared to the (64,32) RS operating at 4,2 Mbits/s.
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- 1.Berlekamp, E., R., "The Technology of Error-Correcting Codes", Proceedings of IEEE, Vol. 68, No. 5, May 1980.Google Scholar
- 2.Berlekamp, E., R., Algebraic Coding Theory, McGraw Hill, New-York: 1968.Google Scholar
- 3.Peterson, W. and Welson, N., Error Correcting Codes, 2nd Edition, The MIT Press, Cambridge, MA: 1972.Google Scholar
- 4.K. Y. Liu, "Architecture for VLSI Design of Reed-Solomon Decoders", IEEETC, Vol. c-33, pp.178–189, Feb. 1984.Google Scholar
- 5.Georges C. Clark and J. Bibb Cain, Error Correcting Coding For Digital Communication, New-York, NY, Plenum Press, 1981.Google Scholar