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A fault-tolerant binary tree architecture

  • Siu-Cheung Chau
  • Arthur L. Liestman
Parallel Processing And Systems
Part of the Lecture Notes in Computer Science book series (LNCS, volume 497)

Abstract

A new fault-tolerant binary tree architecture is proposed. The approach, employing redundant processors, is suitable for use in long-life unmaintained applications. In our proposed scheme, processors connected as n level full binary tree, are backed up by k spare processors so that the fault-tolerant binary tree can tolerate any set of k faults. This new scheme is compared to previously proposed fault-tolerant binary tree architectures. In particular, we show that the new scheme can achieve the same level of reliability as other proposed scheme while using significantly fewer spares.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1991

Authors and Affiliations

  • Siu-Cheung Chau
    • 1
  • Arthur L. Liestman
    • 2
  1. 1.Dept. of Mathematics and Computer ScienceUniversity of LethbridgeLethbridgeCanada
  2. 2.School of Computing ScienceSimon Fraser UniversityBurnabyCanada

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