# Two polynomial problems in PLA folding

VLSI Layout

First Online:

## Abstract

Block-folding and variable-folding are widely used techniques for reducing the physical area of Programmed Logic Arrays (PLA). Both block- and variable-folding problems are known to be NP-hard. We define the compatibility graph of a PLA as the complement of its column-disjoint graph, and prove that both block-folding and variable-folding can be solved in polynomial time on PLA whose compatibility graph does not contain a claw or a (K_{5} − e) as induced subgraph.

## Preview

Unable to display preview. Download preview PDF.

## References

- [1]C. Arbib, M. Lucertini, S. Nicoloso (1990): "Polynomial and NP-complete problems in Programmed Logic Arrays Folding", CNR, Istituto di Analisi dei Sistemi e Informatica, R. 284., January 1990.Google Scholar
- [2]D.D. Caviglia, V. Piuri, M. Santomauro (1987): "About Folded-PLA Area and Folding Evaluation",
*Integration*, 5, pp. 193–215.Google Scholar - [3]G. De Micheli, M. Santomauro (1983): "Topological Partitioning of Programmable Logic Arrays",
*Int. Conf. on Computer Aided Design*.Google Scholar - [4]N. Deo, M.S. Krishnamoorthy, M.A. Langston (1987): "Exact and Approximate Solutions for the Gate Matrix Layout Problem",
*IEEE Trans. on Computer-Aided-Design*, CAD-6, 1, pp.79–84.Google Scholar - [5]J.R. Egan, C.L. Liu (1984): "Bipartite Folding and Partitioning of a PLA",
*IEEE Trans. on Computer-Aided-Design*, CAD-3, 3, pp. 191–199.Google Scholar - [6]P. Erdös (1961): "Graph Theory and Probability, II",
*Canadian J. Math.*, 13, pp.346–352.Google Scholar - [7]H. Fleisher, L.I. Maissel (1975): "An Introduction to Array Logic",
*IBM J. Res. Develop.*, 3, pp.98–109.Google Scholar - [8]D.L. Greer (1976): "An Associative Logic Matrix",
*IEEE J. of Solid-State Circuits*, SC-11, 5, pp.679–691.Google Scholar - [9]G.D. Hachtel, A.R. Newton, A.L. Sangiovanni-Vincentelli (1980): "Some Results in Optimal PLA Folding",
*Proc. Int. Conf. on Circuits and Computers*, pp. 1023–1027.Google Scholar - [10]G.D. Hachtel, A.R. Newton, A.L. Sangiovanni-Vincentelli (1982): "Techniques for Programmable Logic Arrays Folding",
*Proc. 19th Design Automation Conf.*, pp.147–155.Google Scholar - [11]F. Harary (1969):
*Graph Theory*, Addison-Wesley Publ. Co. (Reading, MA), p. 16.Google Scholar - [12]T.C. Hu, Y.S. Kuo (1987): "Graph Folding and PLA",
*Networks*, 17, pp.19–37.Google Scholar - [13]S.Y. Hwang, R.W. Dutton, T. Blank (1986): "A Best-first Search Algorithm for Optimal PLA Folding",
*IEEE Trans. on Computer-Aided-Design*, CAD-5, 3, pp. 433–442.Google Scholar - [14]Y.S. Kuo, T.C. Hu (1987): "An Effective Algorithm for Optimal PLA Column Folding",
*Integration*, 5, pp. 217–230.Google Scholar - [15]J.L. Lewandowsky, C.L. Liu (1984): "A Branch and Bound Algorithm for Optimal PLA Folding",
*Proc. 21th Design Automation Conf.*, pp.426–433.Google Scholar - [16]M. Luby, V. Vazirani, U. Vazirani, A.L. Sangiovanni-Vincentelli (1982): "Some Theoretical Results on the Optimal PLA Folding Problem",
*Proc. IEEE Int. Symp. on Circuits and Systems*, pp. 165–170.Google Scholar - [17]C. Mead, L. Conway (1980):
*Introduction to VLSI Systems*, Addison Wesley Publ. Co. (Reading, MA) pp. 79–82.Google Scholar - [18]R.H. Möhring (1989): "Graph Problem Related to Gate Matrix Layout and PLA Folding", preprint Technische Univ. Berlin, and
*Computing*, to appear.Google Scholar - [19]R. Müller, D. Wagner (1989): "Minimum Vertex Separation into Bounded Sets is NP-hard even for 3-regular Graphs", preprint Technische Univ. Berlin.Google Scholar
- [20]S. Nicoloso, M.L. Sales (1989): "The PLA Folding Problem: Simulated Annealing and Iterative Improvement Approaches",
*Proc. IFIP Conf. on System Modelling and Optimization*, to appear.Google Scholar - [21]S.S. Ravi, E.L. Lloyd (1988): "The Complexity of Near-optimal PLA-folding",
*SIAM Journal on Computing*, 17.Google Scholar - [22]D.F. Wong, H.W. Leong, C.L. Liu (1987): "PLA Folding by Simulated Annealing",
*IEEE J. of Solid State Circuits*, SC-22, 2, pp. 208–215.Google Scholar - [23]R.A. Wood (1979): "A High Density Programmable Logic Array Chip",
*IEEE Trans. on Computing*, C-28, 9, pp. 602–608.Google Scholar

## Copyright information

© Springer-Verlag Berlin Heidelberg 1991