Design and simulation of a multistage interconnection network
An interconnection network for a high-performance parallel computer for database, Lisp and Prolog applications is currently being developed. To meet the requirements derived from applications a multistage interconnection network is chosen. The selection of the switching elements and their optimization was done by simulation with randomly distributed load patterns as well as with traces from applications. The proposed network is composed of 8 × 8 crossbar switches with four independent packet buffers per input port. Each switch will be contained in a single VLSI-chip. The network will operate with a bandwidth of 20 Mbytes/sec on each communication channel.
Key Wordsbuffering scheme crossbar switch delta network network simulation parallel computer virtual cut-through
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