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International Conference on Vector and Parallel Processing

International Conference on Parallel Processing

VAPP 1990, CONPAR 1990: CONPAR 90 — VAPP IV pp 288–299Cite as

Cedar Fortrand its compiler

  • Compile-Time Analysis And Restructurers
  • Conference paper
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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 457))

Abstract

The Cedar architecture integrates shared memory with a distributed system of Alliant mini-supercomputers. Nested parallel loops and a hierarchical memory model allow Cedar Fortran to offer a wide range of implementation possibilities for an algorithm, which makes automatic parallelization easy to do, but hard to do well. Techniques from both shared memory and distributed memory programming paradigms are applied to this problem.

This work was supported by the U.S. Department of Energy under Grant No. DOE DE-FG02-85ER25001

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Author information

Authors and Affiliations

  1. Center for Supercomputing Research and Development, University of Illinois at Urbana-Champaign, 61801, Urbana, Illinois

    R. Eigenmann, J. Hoeflinger, G. Jaxon & D. Padua

Authors
  1. R. Eigenmann
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  2. J. Hoeflinger
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  3. G. Jaxon
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  4. D. Padua
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Editor information

Helmar Burkhart

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© 1990 Springer-Verlag Berlin Heidelberg

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Eigenmann, R., Hoeflinger, J., Jaxon, G., Padua, D. (1990). Cedar Fortrand its compiler. In: Burkhart, H. (eds) CONPAR 90 — VAPP IV. VAPP CONPAR 1990 1990. Lecture Notes in Computer Science, vol 457. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-53065-7_108

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  • DOI: https://doi.org/10.1007/3-540-53065-7_108

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-53065-7

  • Online ISBN: 978-3-540-46597-3

  • eBook Packages: Springer Book Archive

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